CY3130R62 Cypress Semiconductor Corp., CY3130R62 Datasheet

CY3130R62

Manufacturer Part Number

CY3130R62

Description

Warp Enterprise VHDL PC

Manufacturer

Cypress Semiconductor Corp.

Datasheet

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Cypress Semiconductor Corporation

Document #: 38-03050 Rev. *A

Features

Note:

• VHDL (IEEE 1076 and 1164) high-level language com-

• Several design entry methods support high-level and

• Language Assistant library of VHDL templates

• Flow Manager Interface to keep track of complex

• UltraGen™ Synthesis and Fitting Technology:

• Support for all Cypress Programmable Logic Devices

pilers with the following features:

low-level design descriptions:

projects

— Designs are portable across multiple devices

— Facilitates the use of industry-standard simulation

— Support for functions and libraries facilitating

— Support for enumerated types, operator overload-

— Graphical HDL Block Diagram editor with a library of

— Aldec Active-HDL™ FSM graphical Finite State

— Behavioral VHDL (IF...THEN...ELSE; CASE...)

— Boolean

— Structural VHDL

— Designs can include multiple entry methods (but

— Infers “modules” such as adders, comparators, etc.,

— User-selectable speed and/or area optimization on a

— Perfectly integrated synthesis and fitting

— Automatic selection of optimal flip-flop type

— Automatic pin assignment

— PSI™ (Programmable Serial Interface™)

— Delta39K™ CPLDs

— Quantum38K™ CPLDs

— Ultra37000™ CPLDs

— F

— MAX340™ CPLDs

— Industry standard PLDs (16V8, 20V8, 22V10)

Cypress reserves the right to substitute prototype boards based on product availability.

and/or EDA environments

and synthesis tools for board- and system-level de-

sign

modular design methodology

ing, For... Generate statements and Integers

blocks and a text-to-block conversion utility from

Aldec

Machine editor

only one HDL) in a single design.

from behavioral descriptions and replaces them with

circuits pre-optimized for the target device.

block-by-block basis

(D type/T type)

LASH

370i™ CPLDs

•

Warp Enterprise™ VHDL CPLD Software

3901 North First Street

Functional Description

Warp Enterprise™ is an integration of the Warp Profession-

al™ CPLD Development package with additional sophisticat-

ed EDA software features from Aldec. In addition to accepting

IEEE 1076/1164 VHDL text and graphical finite state machines

for design entry, Warp Enterprise VHDL provides a graphical

HDL block diagram editor with a library of graphical HDL

blocks pre-optimized for Cypress devices. Plus, it provides a

utility to convert HDL text into graphical HDL blocks. Warp

Enterprise synthesizes and optimizes the entered design, and

outputs a JEDEC or Intel hex file for the desired PLD or CPLD

(see Figure 1). For simulation, Warp Enterprise provides a tim-

ing simulator, a source-level behavioral simulator, as well as

VHDL and Verilog timing models for use with third party simu-

lators. Warp Enterprise also provides the designer with impor-

tant productivity tools such as a testbench generation wizard

and the Architecture Explorer graphical analysis tool.

• VHDL or Verilog timing model output for use with

• Timing simulation provided by Active-HDL™ Sim

• Architecture Explorer and Dynamic Timing Simulator

• Static Timing Report for all devices

• Source-Level Behavioral Simulation and Debugger

• Testbench Generation

• UltraISR Programming Cable

• Delta39K\Ultra37000 prototype board with a CY37256V

• On-line documentation and help

third-party simulators

Release 4.1 from Aldec

for PSI, Delta39K and Quantum38K devices:

from Aldec

160-pin TQFP device and a CY39100V 208-pin PQFP

device

— Graphical waveform simulator

— Graphical entry and modification of all waveforms

— Ability to compare waveforms and highlight differ-

— Ability to probe internal nodes

— Display of inputs, outputs, and high-impedance (Z)

— Automatic clock and pulse creation

— Support for buses

— Unlimited simulation time

— Graphical representation of exactly how your design

— Zoom from the device level down to the macrocell

— Determine the timing for any path and view that path

ences before and after a design change

signals in different colors

will be implemented on your specific target device

level

on a graphical representation of the chip

•

[1]

San Jose

•

CA 95134

Revised January 9, 2002

•

408-943-2600

CY3130

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