tza3015hw NXP Semiconductors, tza3015hw Datasheet - Page 25

• Manufacturer Part Number: tza3015hw
• Description: 30 Mbit/s To 3.2 Gbit/s A-rate 4-bit Fibre Optic Transceiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Clean-up loop back mode
The TZA3015HW can be used in transponder
applications. In this application, the transmitter is locked
onto the recovered clock from the DCR (RXPRSCL).
Without preparations, the jitter transfer of this application is
determined by cascading the transfer functions of the DCR
and the clock synthesizer. This transfer function is not well
controlled and may not meet the required specification in
terms of bandwidth and/or jitter peaking. A second
drawback is that the jitter generation of the synthesizer is
degraded because the frequency reference (i.e. the DCR)
is not very clean in terms of phase-noise.
To improve both the jitter transfer and jitter generation in
transponder applications, an external low-noise reference
oscillator is locked onto the DCR recovered clock by
means of a small band PLL, i.e. the clean-up PLL. The
low-noise oscillator, e.g. a Voltage Controlled Crystal
Oscillator (VCXO), acts as the reference for the clock
synthesizer. If appropriately designed, the jitter will be
dominated by the clean-up PLL. This PLL can be
optimized for bandwidth and jitter peaking, while the jitter
generation is optimized by choosing the appropriate
VCXO.
Figure 20 shows a typical clean-up PLL application. For
ease of use, all components are integrated in the
TZA3015HW, except for the VCXO and the loop filter
2003 Dec 16
handbook, full pagewidth
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
serial
serial
serial
clock
data
data
LIMITER
DCR
Fig.19 Serial loop timing mode.
clock
clock
data
data
MULTIPLEXER
25
components. The PLL consists of a phase frequency
detector, a charge pump, an external loop filter (R, C1 and
C2), a VCXO and a reference divider. The combination of
R and C1 is mandatory and will transform the current at the
output of the charge pump into a control voltage for the
VXCO. Capacitor C2 is optional.
The internal clock and data path in the TZA3015HW is
clarified in Fig.21. As can be seen in the clean-up
application, the received (and transmitted) data is also
available in parallel format at the parallel output bus.
Two bits are available to ease the design of the clean-up
PLL. The loop is designed to work with a VCXO that has a
positive gain. That is an increasing voltage on the VCXO
control input will increase the output frequency. By means
of bit CLUPPLLINV of register REFDIV (A1h) the loop is
inverted and will work with VCXOs which have a negative
gain. Bit CLUPPLLHG of register REFDIV (A1h) will
change the gain of the charge pump. If bit CLUPPLLHG is
logic 0, the charge pump current I
CLUPPLLHG is logic 1, the charge pump current I
1 mA. This eases choosing suitable component values for
R and C1.
DEMULTIPLEXER
SYNTHESIZER
4
4
4
4
4
Preliminary specification
CP
TZA3015HW
parallel
data
parallel
clock
parallel
data
parallel
clock
MCE418
is 100 A. If bit
CP
is