tza3015hw NXP Semiconductors, tza3015hw Datasheet - Page 11

• Manufacturer Part Number: tza3015hw
• Description: 30 Mbit/s To 3.2 Gbit/s A-rate 4-bit Fibre Optic Transceiver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
D
The TZA3015HW recovers the clock and data contents
from the incoming bit stream; see Fig.6. The DCR uses a
combined frequency and phase locking scheme, providing
reliable and quick data acquisition on any bit rate between
30 Mbit/s and 3.2 Gbit/s.
At power-up, coarse adjustment of the free running
Voltage Controlled Oscillator (VCO) frequency is required.
This is achieved by the Frequency Window Detector
(FWD) circuit. The FWD is a conventional frequency
locked PLL. The FWD checks the VCO frequency, which
has to be within a 1000 ppm window around the required
frequency. The FWD then compares the divided VCO
frequency, also available on pins RXPRSCL(Q), with the
reference frequency on pins CREF(Q), usually 19.44 MHz.
If the VCO frequency is outside this window, the FWD
disables the Data Phase Detector (DPD) and forces the
VCO to a frequency within the window. As soon as the ‘in
window’ condition occurs, which is visible on pin
INWINDOW, the DPD is enabled and will lock on the
incoming bit stream. Since the VCO frequency is very
close to the expected bit rate, the phase acquisition will be
almost instantaneous, resulting in quick phase lock to the
incoming data stream.
Although the VCO is now locked to the incoming bit
stream, the FWD is still supervising the VCO frequency
2003 Dec 16
handbook, full pagewidth
ATA AND
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
C
amplifier and
from limiting
LOCK
DLB MUX
CREF(Q)
divided
R
ECOVERY
DIVIDER N, K
REFERENCE
DIVIDER
OCTAVE
DIVIDER
(DCR)
MAIN
Fig.6 Functional diagram of data and clock recovery.
Frac
M
N
INWINDOW
CONTROLLED
DATA PHASE
OSCILLATOR
FREQUENCY
DETECTOR
DETECTOR
VOLTAGE
WINDOW
WINSIZE
down
down
11
up
up
and takes over control if the VCO frequency drifts outside
the predefined frequency window. This might occur during
a ‘loss of signal’ situation. Due to the FWD, the VCO
frequency is always close to the required bit rate, enabling
rapid phase acquisition when the lost input signal returns.
Due to the loose coupling of 1000 ppm, the reference
frequency does not need to be highly accurate or stable.
Any crystal-based oscillator that generates a reasonably
accurate frequency (e.g. 100 ppm) will do. This only holds
if the TZA3015HW is used as a receiver since the
synthesizer of the transmitter uses the same reference
clock. The transmitter does need a very accurate
reference frequency.
Fractional N synthesizer in the DCR
The DCR section contains a fractional N synthesizer as
frequency acquisition aid for the A-rate functionality. This
allows the DCR to synchronize on incoming data,
regardless of the received bit rate. Any combination of bit
rate and reference frequency is possible, due to the 22 bits
fractional N synthesizer, allowing approximately 10 Hz
frequency resolution. The LSB (bit K0) should be set to
logic 1 to avoid limit cycles (cycles of less than maximum
length). This leaves 21 bits (bits K[21:1]), available for free
programming.
CHARGE PUMP
CHARGE PUMP
LOOP FILTER
recovered clock
recovered data
PRESCALER BUFFER
to
demultiplexer
Preliminary specification
MGU683
TZA3015HW
RXPRSCL(Q)