sg6741tp Fairchild Semiconductor, sg6741tp Datasheet - Page 9

• Manufacturer Part Number: sg6741tp
• Description: Sg6741-highly-integrated Green-mode Pwm Controller
• Manufacturer: Fairchild Semiconductor

Highly-Integrated Green-Mode PWM Controller
Operation Description
Start-up Current
For start-up, the HV pin is connected to the line input or
bulk capacitor through an external resistor, R
recommended as 100KΩ. Typical start-up current drawn
from pin HV is 2mA and it charges the hold-up capacitor
through the resistor R
reaches V
moment, the V
maintain the V
transformer to carry on provide the operating current.
Operating Current
Operating current is around 4mA. The low operating
current enables better efficiency and reduces the
requirement of V
Green-Mode Operation
The patented green-mode function provides an off-time
modulation to reduce switching frequency in light-load
and no-load conditions. The on time is limited for better
abnormal or brownout protection. VFB, which is derived
from the voltage feedback loop, is used as the reference.
Once VFB is lower than the threshold voltage, switching
frequency is continuously decreased to the minimum
green-mode frequency, around 22KHz (R
Oscillator Operation
A resistor connected from the RI pin to GND generates a
constant current source for the SG6741 controller. This
current is used to determine the center PWM frequency.
Increasing the resistance reduces PWM frequency. Using
a 26KΩ resistor, R
PWM frequency. The relationship between R
switching frequency is:
as 47kHz ~ 109kHz.
© System General Corp.
Version 1.3.1 (IAO33.0047.B3)
The range of the PWM oscillation frequency is designed
f
PWM
=
R
DD-ON
1690
I
(K
Ω
DD
, the start-up current switches off. At that
DD
)
DD
before the auxiliary winding of the main
(KHz)
capacitor only supplies the SG6741 to
hold-up capacitance.
I
, results in a corresponding 65KHz
HV
---------------------
. When the V
DD
I
=26KΩ).
capacitor level
HV
, which is
I
and the
(1)
- 9 -
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized in SG6741 to
regulate output voltage and provide pulse-by-pulse
current limiting. The switch current is detected by a sense
resistor into the SENSE pin. The PWM duty cycle is
determined by this current-sense signal and V
feedback voltage. When the voltage on the SENSE pin
reaches around V
terminated immediately. V
variable voltage around 0.85V for output power limit.
Leading-Edge Blanking
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch off
the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at
16.5V/10.5V. During start-up, the hold-up capacitor must
be charged to 16.5V through the start-up resistor so that
IC is enabled. The hold-up capacitor continues to supply
V
winding of the main transformer. V
below 10.5V during this start-up process. This UVLO
hysteresis window ensures that hold-up capacitor is
adequate to supply V
Gate Output / Soft Driving
The SG6741 BiCMOS output stage is a fast totem pole
gate driver. Cross conduction has been avoided to
minimize heat dissipation, increase efficiency, and
enhance reliability. The output driver is clamped by an
internal 18V Zener diode to protect power MOSFET
transistors against undesirable gate over-voltage. A soft
driving waveform is implemented to minimize EMI.
DD
before the energy can be delivered from auxiliary
www.sg.com.tw • www.fairchildsemi.com
COMP
DD
= (V
during start-up.
COMP
FB
–1.2)/3.2, the switch cycle is
Product specification
is internally clamped to a
DD
October 30, 2007
must not drop
SG6741
FB
, the