mt28f640j3rp-115-met Micron Semiconductor Products, mt28f640j3rp-115-met Datasheet - Page 23

• Manufacturer Part Number: mt28f640j3rp-115-met
• Description: 128mb, 64mb, 32mb Q-flash Memory
• Manufacturer: Micron Semiconductor Products

READ IDENTIFIER CODES Command
initiates the IDENTIFIER CODE operation. Following
the writing of the command, READ cycles from
addresses shown in Figure 7 on page 12 retrieve the
manufacturer, device, and block lock configuration
codes (see Table 16 on page 23 for identifier code val-
ues). Page mode READs are not supported in this read
mode. To terminate the operation, write another valid
command. The READ IDENTIFIER CODES command
functions independently of the V
command is valid only when the ISM is off or the
device is suspended. See Table 16 on page 23 for read
identifier codes.
READ STATUS REGISTER Command
either issue a discrete READ STATUS REGISTER com-
mand or when the ISM is running, a READ of the
device will provide valid status register data. Once the
Table 16: Identifier Codes
NOTE:
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
CODE
Manufacturer’s Identification Code
• Intel ManID
• Micron ManID
Device Code
• 32Mb
• 64Mb
• 128Mb
Block Lock Configuration
• Block is Unlocked
• Block is Locked
• Reserved for Future Use
1. A0 is not used in either x8 or x16 modes when obtaining the identifier codes. The lowest-order address line is A1.
2. Different ManID devices are ordered via separate part numbers. See Figure 4 on page 8 for details.
3. X selects the specific block’s lock configuration code. See Figure 6 on page 11 for the device identifier code memory
Writing the READ IDENTIFIER CODES command
The status register may be read one of two ways:
Data is always presented on the low byte in x16 mode (upper byte contains 00h).
map.
2
PEN
voltage. This
23
device is in this mode, all subsequent READ opera-
tions output data from the status register until another
valid command is written. Page mode READs are not
supported in this read mode.
ing edge of OE# or the first edge of CEx that enables the
device (see Table 2 on page 11). To update the status
register latch, OE# must toggle to V
must be disabled before further READs. The READ
STATUS REGISTER command functions indepen-
dently of the V
erase, set block lock bits, or clear block lock bits com-
mand sequence, only SR7 is valid until the ISM com-
pletes or suspends the operation. Device I/O pins
DQ0–DQ6 and DQ8–DQ15 are placed in High-Z. When
the operation completes or suspends (check status
register bit 7), all contents of the status register are
valid during a READ.
The status register contents are latched on the fall-
ADDRESS
XX0002h
X00000h
X00001h
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
1
PEN
128Mb, 64Mb, 32Mb
voltage. During a program, block
Q-FLASH MEMORY
DQ1–DQ7
DQ0 = 0
DQ0 = 1
(00) 2C
(00) 89
(00) 16
(00) 17
(00) 18
DATA
IH
©2000 Micron Technology. Inc.
or the device