hyb18t512160af-5 Infineon Technologies Corporation, hyb18t512160af-5 Datasheet - Page 15

• Manufacturer Part Number: hyb18t512160af-5
• Description: 512-mbit Ddr2 Sdram
• Manufacturer: Infineon Technologies Corporation

Table 4
Ball#/Pin#
Control Signals ×16 organization
K7
L7
K3
L8
Address Signals ×4/×8 organizations
G2
G3
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
Address Signals ×16 organization
L2
L3
L1
Data Sheet
Pin Configuration of DDR SDRAM
Name
RAS
CAS
WE
CS
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
A13
NC
BA0
BA1
NC
Pin
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
–
I
I
–
SSTL
SSTL
SSTL
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
–
SSTL
SSTL
–
Function
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Chip Select
Bank Address Bus 1:0
Note: BA[1:0] define to which bank an Activate, Read, Write or
Address Signal 12:0, Address Signal 10/Autoprecharge
Note: Address Signal 10/Autoprecharge provides the row address
Address Signal 13
Note: 512 Mbit components
Note: 256 Mbit components
Bank Address Bus 1:0
Precharge command is being applied. BA[1:0] also
determines if the mode register or extended mode register
is to be accessed during a MRS or EMRS(1) cycle
for Activate commands and the column address and Auto-
Precharge bit A10 (=AP) for Read/Write commands to
select one location out of the memory array in the respective
bank. A10(=AP) is sampled during a Precharge command
to determine whether the Precharge applies to one bank
(A10=LOW) or all banks (A10=HIGH). If only one bank is to
be precharged, the bank is selected by BA[1:0]. The
address inputs also provide the op-code during Mode
Register Set commands.
15
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
Pin Configuration and Block Diagrams
512-Mbit DDR2 SDRAM
09112003-SDM9-IQ3P
Rev. 1.3, 2005-01