hyb18t512160bf-5 Infineon Technologies Corporation, hyb18t512160bf-5 Datasheet - Page 9

• Manufacturer Part Number: hyb18t512160bf-5
• Description: 240-pin Unbuffered Ddr2 Sdram Modules
• Manufacturer: Infineon Technologies Corporation

2
The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in
abbreviations used in columns Pin and Buffer Type are explained in
numbering is depicted in
Table 6
Pin or Ball No.
Clock Signals
185
137
220
186
138
221
52
171
Control Signals
193
76
192
74
73
Data Sheet
Pin Configuration and Block Diagrams
Pin Configuration of UDIMM
Name Pin
CK0
CK1
CK2
CK0
CK1
CK2
CKE0
CKE1
NC
S0
S1
NC
RAS
CAS
WE
Figure 1
Type
I
I
I
I
I
I
I
I
NC
I
I
NC
I
I
I
for non-ECC modules (×64) and
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
—
SSTL
SSTL
—
SSTL
SSTL
SSTL
Function
Clock Signals 2:0, Complement Clock Signals 2:0
The system clock inputs. All address and command lines are sampled
on the cross point of the rising edge of CK and the falling edge of CK.
A Delay Locked Loop (DLL) circuit is driven from the clock inputs and
output timing for read operations is synchronized to the input clock.
Clock Enable Rank 1:0
Activates the DDR2 SDRAM CK signal when HIGH and deactivates
the CK signal when LOW. By deactivating the clocks, CKE LOW
initiates the Power Down Mode or the Self Refresh Mode.
Note: 2 Ranks module
Not Connected
Note: 1 Rank module
Chip Select Rank 1:0
Enables the associated DDR2 SDRAM command decoder when
LOW and disables the command decoder when HIGH. When the
command decoder is disabled, new commands are ignored but
previous operations continue. Rank 0 is selected by S0; Rank 1 is
selected by S1. Ranks are also called "Physical banks".
Note: 2 Ranks module
Not Connected
Note: 1 Rank module
Row Address Strobe
When sampled at the cross point of the rising edge of CK,and falling
edge of CK, RAS, CAS and WE define the operation to be executed
by the SDRAM.
Column Address Strobe
Write Enable
9
HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A
Unbuffered DDR2 SDRAM Modules
Figure 2
Table 7
Pin Configuration and Block Diagrams
for ECC modules (×72).
and
Table 8
02182004-DHQB-4RRW
Table 6
respectively. The pin
Rev. 1.3, 2005-09
(240 pins). The