hyb18t512160bf-5 Infineon Technologies Corporation, hyb18t512160bf-5 Datasheet - Page 33

• Manufacturer Part Number: hyb18t512160bf-5
• Description: 240-pin Unbuffered Ddr2 Sdram Modules
• Manufacturer: Infineon Technologies Corporation

Table 23
Parameter
DQS falling edge to CK setup time (write cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh command
period
Precharge-All (4 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command period
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-
Precharge
Write recovery time for write with Auto-Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read command
(slow exit, lower power)
Exit precharge power-down to any valid command
(other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
1) For details and notes see the relevant INFINEON component data sheet
2)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
Data Sheet
V
powered down and then restarted through the specified initialization sequence before normal operation can continue.
DDQ
= 1.8 V ± 0.1 V;
Timing Parameter by Speed Grade - DDR2-533 (cont’d)
V
DD
= 1.8 V ± 0.1 V. See notes
4)5)6)7)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WR
t
t
t
t
t
t
DSS
HP
HZ
IH
IPW
IS
LZ(DQ)
LZ(DQS)
MRD
OIT
QH
QHS
REFI
RFC
RP
RPRE
RPST
RRD
RTP
WPRE
WPST
WR
WTR
XARD
XARDS
XP
XSNR
XSRD
(base)
(base)
33
HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A
DDR2–533
Min.
0.2
MIN. (
—
375
0.6
250
2 °
t
2
0
t
—
—
—
75
t
0.9
0.40
7.5
10
7.5
0.35x
0.40
15
t
7.5
2
6 – AL
2
t
200
AC.MIN
HP
RP
WR
RFC
Unbuffered DDR2 SDRAM Modules
–
/
t
+ 1
t
AC.MIN
CK
+10
t
QHS
t
t
CK
t
CL,
CK
t
CH
)
Max.
—
t
—
—
—
t
t
—
12
—
400
7.8
3.9
—
—
1.1
0.60
—
—
—
—
0.60
—
—
—
—
—
—
—
AC.MAX
AC.MAX
AC.MAX
Electrical Characteristics
02182004-DHQB-4RRW
Rev. 1.3, 2005-09
Unit
t
ps
ps
t
ps
ps
ps
t
ns
ps
µs
µs
ns
ns
t
t
ns
ns
ns
t
t
ns
t
ns
t
t
t
ns
t
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
Note
3)4)5)6)7)
8)
9)
10)
1)11)
1)2)