hyb18t512160bf-5 Infineon Technologies Corporation, hyb18t512160bf-5 Datasheet - Page 16

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hyb18t512160bf-5

Manufacturer Part Number
hyb18t512160bf-5
Description
240-pin Unbuffered Ddr2 Sdram Modules
Manufacturer
Infineon Technologies Corporation
Datasheet
Table 7
Abbreviation
I
O
I/O
AI
PWR
GND
NC
Table 8
Abbreviation
SSTL
LV-CMOS
CMOS
OD
Data Sheet
Abbreviations for Pin Type
Abbreviations for Buffer Type
Description
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
Ground
Not Connected
Description
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and
tri-state, and allows multiple devices to share as a wire-OR.
16
HYS[64/72]T[16/32/64]0xxHU-[2.5/.../5]-A
Unbuffered DDR2 SDRAM Modules
Pin Configuration and Block Diagrams
02182004-DHQB-4RRW
Rev. 1.3, 2005-09

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