lh28f800bje-pttlz1 Sharp Microelectronics of the Americas, lh28f800bje-pttlz1 Datasheet - Page 12

• Manufacturer Part Number: lh28f800bje-pttlz1
• Manufacturer: Sharp Microelectronics of the Americas

3.7 Write
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection and
clearing of the status register. When V
V
erase, full chip erase, word/byte write and lock-bit
configuration.
The Block Erase command requires appropriate command
data and an address within the block to be erased. The Full
Chip Erase command requires appropriate command data
and an address within the device. The Word/Byte Write
command requires the command and address of the
location to be written. Set Permanent and Block Lock-Bit
commands require the command and address within the
device (Permanent Lock) or block within the device
(Block Lock) to be locked. The Clear Block Lock-Bits
command requires the command and address within the
device.
NOTES:
1. Refer to DC Characteristics. When V
2. X can be V
3. RY/BY# is V
4. RP# at GND±0.2V ensures the lowest power consumption.
5. See Section 4.2 for read identifier code data.
6. Command writes involving block erase, full chip erase, word/byte write or lock-bit configuration are reliably executed
7. Refer to Table 3 for valid D
8. Never hold OE# low and WE# low at the same timing.
Read
Output Disable
Standby
Reset
Read Identifier Codes
Write
Read
Output Disable
Standby
Reset
Read Identifier Codes
Write
CCW
V
algorithms. It is High Z during when the WSM is not busy, in block erase suspend mode (with word/byte write inactive),
word/byte write suspend mode or reset mode.
when V
CCWLK
=V
CCWH1/2
Mode
Mode
CCW
voltages.
IL
=V
OL
or V
, the CUI additionally controls block
CCWH1/2
when the WSM is executing internal block erase, full chip erase, word/byte write or lock-bit configuration
IH
for control pins and addresses, and V
and V
Notes
Notes
6,7,8
6,7,8
IN
8
4
8
8
4
8
during a write operation.
CC
=3.1V-3.5V.
CC
Table 2.1. Bus Operations (BYTE#=V
Table 2.2. Bus Operations (BYTE#=V
CCW
RP#
RP#
V
V
V
V
V
V
V
V
V
V
V
V
=3.1V-3.5V and
IH
IH
IH
IH
IH
IH
IH
IH
IH
IH
IL
IL
V
CCWLK
CE#
CE#
V
V
V
V
V
V
V
V
V
V
X
X
IH
IH
IL
IL
IL
IL
IL
IL
IL
IL
, memory contents can be read, but not altered.
CCWLK
OE#
OE#
V
V
V
V
V
V
V
V
X
X
X
X
IH
IH
IH
IH
IL
IL
IL
IL
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active. The
address and data needed to execute a command are latched
on the rising edge of WE# or CE# (whichever goes high
first). Standard microprocessor write timings are used.
Figures 18 and 19 illustrate WE# and CE# controlled write
operations.
4 COMMAND DEFINITIONS
When the V
the status register, identifier codes, or blocks are enabled.
Placing V
erase, full chip erase, word/byte write and lock-bit
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these commands.
or V
WE#
WE#
V
V
V
V
V
V
V
V
X
X
X
X
IH
IH
IH
IH
IH
IH
CCWH1/2
IL
IL
CCWH1/2
IH
IL
Figure 4, 5
Figure 4, 5
CCW
Address
Address
)
)
(1,2)
(1,2)
for V
See
See
X
X
X
X
X
X
X
X
X
X
voltage V
CCW
on V
. See DC Characteristics for
V
V
CCW
CCW
CCW
X
X
X
X
X
X
X
X
X
X
X
X
CCWLK
enables successful block
, read operations from
DQ
High Z
High Z
High Z
High Z
High Z
High Z
Note 5
Note 5
DQ
D
D
D
D
OUT
OUT
IN
IN
0-15
0-7
RY/BY#
RY/BY#
High Z
High Z
High Z
High Z
Rev. 1.27
X
X
X
X
X
X
X
X
(3)
(3)