w25q16bv Winbond Electronics Corp America, w25q16bv Datasheet - Page 13
![no-image](/images/no-image-200.jpg)
w25q16bv
Manufacturer Part Number
w25q16bv
Description
16m-bit Serial Flash Memory With Dual And Quad Spi
Manufacturer
Winbond Electronics Corp America
Datasheet
1.W25Q16BV.pdf
(65 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
w25q16bvCC3
Manufacturer:
WINBOND/华邦
Quantity:
20 000
Part Number:
w25q16bvFCC3
Manufacturer:
WINBOND/华邦
Quantity:
20 000
Company:
Part Number:
w25q16bvIG
Manufacturer:
WINBOND
Quantity:
10 549
Part Number:
w25q16bvNIG
Manufacturer:
WINBOND/华邦
Quantity:
20 000
Company:
Part Number:
w25q16bvSIG
Manufacturer:
JMICRON
Quantity:
1 000
Part Number:
w25q16bvSIG
Manufacturer:
WINOND
Quantity:
20 000
Company:
Part Number:
w25q16bvSS1G
Manufacturer:
SemiHow
Quantity:
16 000
Company:
Part Number:
w25q16bvSSIG
Manufacturer:
WINBOND
Quantity:
9 270
Company:
Part Number:
w25q16bvSSIG
Manufacturer:
WINBOND
Quantity:
20 655
Part Number:
w25q16bvSSIG
Manufacturer:
WINBOND/华邦
Quantity:
20 000
10.1.6 Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register
(S8 and S7). The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable (OTP) protection.
Note:
1. These features are available upon special order. Please refer to Ordering Information.
2. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
10.1.7 Erase Suspend Status (SUS)
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing an
Erase Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase Resume (7Ah) instruction
as well as a power-down, power-up cycle.
10.1.8 Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad
operation. When the QE bit is set to a 0 state (factory default) the /WP pin and /Hold are enabled. When
the QE bit is set to a 1 the Quad IO2 and IO3 pins are enabled.
WARNING: The QE bit should never be set to a 1 during standard SPI or Dual SPI operation if the
/WP or /HOLD pins are tied directly to the power supply or ground.
SRP1
0
0
0
1
1
SRP0
0
1
1
0
1
/WP
X
X
X
0
1
Power Supply
Lock-Down
Unprotected
Program
Protection
One Time
Hardware
Protected
Hardware
Register
Software
Status
(1)
(1)
Description
/WP pin has no control. The Status register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
When /WP pin is low the Status Register locked and can not
be written to.
When /WP pin is high the Status register is unlocked and can
be written to after a Write Enable instruction, WEL=1.
Status Register is protected and can not be written to again
until the next power-down, power-up cycle.
Status Register is permanently protected and can not be
written to.
- 13 -
Publication Release Date: March 13, 2009
Preliminary - Revision B
W25Q16BV
(2)