m24c32-wmn3p STMicroelectronics, m24c32-wmn3p Datasheet - Page 6
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m24c32-wmn3p
Manufacturer Part Number
m24c32-wmn3p
Description
Kbit, Kbit Kbit Serial Eeprom
Manufacturer
STMicroelectronics
Datasheet
1.M24C32-WMN3P.pdf
(34 pages)
Summary description
1
6/34
Summary description
The M24C32, M24C64 and M24128 devices are I
programmable memories (EEPROM). They are organized as 4096 × 8 bits, 8192 × 8 bits
and 16384 × 8 bits, respectively.
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages.
ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 1.
I
The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the
I
The device behaves as a slave in the I
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a Device Select Code and Read/Write
bit (RW) (as described in
When writing data to the memory, the device inserts an acknowledge bit during the 9
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
2
2
C uses a two-wire serial interface, comprising a bi-directional data line and a clock line.
C bus definition.
Logic diagram
Table
E0-E2
SCL
WC
3), terminated by an acknowledge bit.
3
2
C protocol, with all memory operations synchronized
V CC
M24128-BW
M24128-BR
M24C64-W
M24C32-W
M24C64-R
M24C32-R
V SS
M24C64-F
M24C32-F
2
C-compatible electrically erasable
SDA
AI01844d
M24128, M24C64, M24C32
th
bit