74abt16244csscx-nl Fairchild Semiconductor, 74abt16244csscx-nl Datasheet

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74abt16244csscx-nl

Manufacturer Part Number
74abt16244csscx-nl
Description
74abt16244 16-bit Buffer/line Driver With 3-state Outputs
Manufacturer
Fairchild Semiconductor
Datasheet
© 2005 Fairchild Semiconductor Corporation
74ABT16244CSSC
74ABT16244CMTD
74ABT16244
16-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ABT16244 contains sixteen non-inverting buffers with
3-STATE outputs designed to be employed as a memory
and address driver, clock driver, or bus oriented transmit-
ter/receiver. The device is nibble controlled. Individual 3-
STATE control inputs can be shorted together for 8-bit or
16-bit operation.
Ordering Code:
Devices are also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Order Number
OE
I
O
Pin Names
0
–I
0
–O
n
15
15
Output Enable Inputs (Active LOW)
Inputs
Outputs
Package Number
MS48A
MTD48
Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS010985
Features
Connection Diagram
Separate control logic for each nibble
16-bit version of the ABT244
Outputs sink capability of 64 mA, source capability of
32 mA
Guaranteed output skew
Guaranteed multiple output switching specifications
Output switching specified for both 50 pF and
250 pF loads
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Non-destructive hot insertion capability
Package Description
April 1992
Revised May 2005
www.fairchildsemi.com

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74abt16244csscx-nl Summary of contents

Page 1

... Inputs –O Outputs 0 15 © 2005 Fairchild Semiconductor Corporation Features Separate control logic for each nibble 16-bit version of the ABT244 Outputs sink capability of 64 mA, source capability Guaranteed output skew Guaranteed multiple output switching specifications Output switching specified for both 50 pF and ...

Page 2

Truth Tables Inputs OE I – Inputs OE I – Inputs OE I – ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2)  Input Current (Note Voltage Applied to Any Output in the Disabled ...

Page 4

DC Electrical Characteristics Symbol Parameter V Quiet Output Maximum Dynamic V OLP OL V Quiet Output Minimum Dynamic V OLV OL V Minimum HIGH Level Dynamic Output Voltage OHV V Minimum HIGH Level Dynamic Input Voltage IHD V Maximum LOW ...

Page 5

Skew Symbol Parameter t Pin to Pin Skew OSHL (Note 13) HL Transitions t Pin to Pin Skew OSLH (Note 13) LH Transitions t Duty Cycle PS (Note 14) LH–HL Skew t Pin to Pin Skew OST (Note 13) LH/HL ...

Page 6

AC Loading *Includes jig and probe capacitance FIGURE 1. Standard AC Test Load Amplitude 3.0V FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 5. Propagation Delay, Pulse Width Waveforms ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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