clc1010 Cadeka Microcircuits LLC., clc1010 Datasheet - Page 11

• Manufacturer Part Number: clc1010
• Description: 70?a, Low Cost, +2.7v & +5v, 7.3mhz Rail-to-rail Amplifers
• Manufacturer: Cadeka Microcircuits LLC.

Advance Data Sheet
For a given load capacitance, adjust R
tradeoff between settling time and bandwidth. In general,
reducing R
additional overshoot and ringing.
Overdrive Recovery
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for
the amplifier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range is
exceeded. The CLC1010 and CLC2010 will typically recover
in less than 60ns from an overdrive condition. Figure 7
shows the CLC1010 in an overdriven condition.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CaDeKa has evaluation
boards to use as a guide for high frequency layout and as
an aid in device testing and characterization. Follow the
steps below as a basis for high frequency layout:
©2009 CADEKA Microcircuits LLC
C
100pF
10pF
20pF
50pF
L
(pF)
S
Table 1: Recommended R
will increase bandwidth at the expense of
Figure 7. Overdrive Recovery
R
TBD
TBD
TBD
TBD
S
(Ω)
-3dB BW (kHz)
S
vs. C
S
to optimize the
L
▪
▪
▪
▪
▪
Refer to the evaluation board layouts below for more
information.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in
Figures 8-14. These evaluation boards are built for dual-
supply operation. Follow these steps to use the board in a
single-supply application:
1. Short -Vs to ground.
2. Use C3 and C4, if the -V
CEB002
CEB003
CEB006
CEB010
Evaluation Board
Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
Place the 6.8µF capacitor within 0.75 inches of the power pin
Place the 0.1µF capacitor within 0.1 inches of the power pin
Remove the ground plane under and around the part,
especially near the input and output pins to reduce
parasitic capacitance
Minimize all trace lengths to reduce series inductances
directly connected to the ground plane.
#
CLC1010 in SOT23
CLC1010 in SOIC
CLC2010 in SOIC
CLC2010 in MSOP
S
pin of the amplifier is not
Products
www.cadeka.com
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