clc1002 Cadeka Microcircuits LLC., clc1002 Datasheet - Page 14

• Manufacturer Part Number: clc1002
• Description: Ultra-low Noise Amplifer
• Manufacturer: Cadeka Microcircuits LLC.

Data Sheet
external resistor noise terms for R
High source impedances are sometimes unavoidable, but
they increase noise from the source impedance and also
make the circuit more sensitive to the op amp current
noise. Analyze all noise sources in the circuit, not just the
op amp itself, to achieve low noise in your application.
Power Dissipation
Power dissipation should not be a factor when operating
under the stated 500Ω load condition. However,
applications with low impedance, DC coupled
should be analyzed to ensure that maximum allowed
junction temperature is not exceeded. Guidelines listed
below can be used to verify that the particular application
will not cause the device to operate beyond it’s intended
operating range.
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction
temperature, the package thermal resistance value
Theta
dissipation.
Where T
In order to determine P
needs to be subtracted from the total power delivered by
the supplies.
Supply power is calculated by the standard power
equation.
Power delivered to a purely resistive load is:
The effective load resistor (Rload
the effect of the feedback network. For instance, Rload
©2007-2008 CADEKA Microcircuits LLC
+ e
2
Rs
JA
Ambient
1 +
(Ө
JA
R
R
T
) is used along with the total die power
g
f
Junction
P
P
is the temperature of the working environment.
load
supply
2
+ e
= ((V
P
V
D
supply
= T
= V
2
Rg
= P
D
, the power dissipated in the load
LOAD
Ambient
supply
R
R
supply
= V
f
g
)
2
RMS
S+
× I
+ e
- P
+ (Ө
- V
2
eff
RMS supply
S
)/Rload
load
, R
2
Rf
) will need to include
S-
JA
g
× P
external resistor noise terms for Rs, Rg and Rf
and R
eff
D
)
f
loads
eff
in figure 3 would be calculated as:
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Here, P
Quiescent power can be derived from the specified I
values along with known supply voltage, V
power can be calculated as above with the desired signal
amplitudes using:
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
Assuming the load is referenced in the middle of the
power rails or V
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the packages
available.
Driving Capacitive Loads
Increased phase delay at the output due to capacitive loading
can cause ringing, peaking in the frequency response, and
possible unstable behavior. Use a series resistance, R
between the amplifier and the load to help improve stability
and settling performance. Refer to Figure 5.
2.5
1.5
0.5
2
1
0
-40
P
D
DYNAMIC
can be found from
( I
SOT23-6
Figure 4. Maximum Power Derating
-20
P
LOAD
D
= P
supply
(V
= (V
)
0
RMS
LOAD
Quiescent
SOIC-8
/2.
Ambient Temperature (°C)
S+
R
= ( V
L
)
20
RMS
- V
|| (R
LOAD
+ P
LOAD
= V
40
f
+ R
Dynamic
)
PEAK
)
RMS
RMS
g
60
)
/ √2
× ( I
/ Rload
- P
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80
Load
LOAD
eff
100
Supply
)
RMS
. Load
120
14
S
S
,