mk50n512cmc100 Freescale Semiconductor, Inc, mk50n512cmc100 Datasheet - Page 63

• Manufacturer Part Number: mk50n512cmc100
• Description: Arm Cortex-m4 Core With Dsp K50 Sub-family Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

8 Pinout
8.1 K50 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
Freescale Semiconductor, Inc.
MAP
BGA
121
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PTE0
PTE1
PTE2
PTE3
PTE4
PTE5
PTE6
VDD
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1/
OP0_DP0
ADC0_DM1/
OP0_DM0
ADC1_DP1/
OP1_DP0/
OP1_DM1
ADC1_DM1/
OP1_DM0
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
Pin Name
ADC1_SE4a ADC1_SE4a PTE0
ADC1_SE5a ADC1_SE5a PTE1
ADC1_SE6a ADC1_SE6a PTE2
ADC1_SE7a ADC1_SE7a PTE3
DISABLED
DISABLED
DISABLED
VDD
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1/
OP0_DP0
ADC0_DM1/
OP0_DM0
ADC1_DP1/
OP1_DP0/
OP1_DM1
ADC1_DM1/
OP1_DM0
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
Default
VDD
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1/
OP0_DP0
ADC0_DM1/
OP0_DM0
ADC1_DP1/
OP1_DP0/
OP1_DM1
ADC1_DM1/
OP1_DM0
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
ALT0
PTE4
PTE5
PTE6
ALT1
SPI1_PCS1
SPI1_SOUT
SPI1_SCK
SPI1_SIN
SPI1_PCS0
SPI1_PCS2
SPI1_PCS3
ALT2
Preliminary
UART1_TX
UART1_RX
UART1_CTS
_b
UART1_RTS
_b
UART3_TX
UART3_RX
UART3_CTS
_b
ALT3
SDHC0_D1
SDHC0_D0
SDHC0_DCL
K
SDHC0_CM
D
SDHC0_D3
SDHC0_D2
I2S0_MCLK
ALT4
ALT5
I2C1_SDA
I2C1_SCL
I2S0_CLKIN
ALT6
ALT7
EzPort
Pinout
63