mk50n512cmc100 Freescale Semiconductor, Inc, mk50n512cmc100 Datasheet - Page 33

• Manufacturer Part Number: mk50n512cmc100
• Description: Arm Cortex-m4 Core With Dsp K50 Sub-family Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Freescale Semiconductor, Inc.
and FB_TS.
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Num
FB1
FB2
FB3
FB4
FB5
Operating voltage
Frequency of operation
Clock period
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
Description
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Table 23. Flexbus switching specifications
EP3
EP5
Figure 9. EzPort Timing Diagram
EP6
EP4
EP7
Preliminary
EP8
EP9
Peripheral operating requirements and behaviors
TBD
Min.
EP2
2.7
8.5
0.5
20
—
0
Max.
11.5
3.6
50
—
—
—
—
Mhz
Unit
ns
ns
ns
ns
ns
V
Notes
1
1
2
2
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