mk50n512cmc100 Freescale Semiconductor, Inc, mk50n512cmc100 Datasheet - Page 19

• Manufacturer Part Number: mk50n512cmc100
• Description: Arm Cortex-m4 Core With Dsp K50 Sub-family Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

5.2.1 Device clock specifications
5.2.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CMT, and I
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75pF load
Freescale Semiconductor, Inc.
f
FB_CLK
FB_CLK
Symbol
Symbol
SYS_USB
f
f
FLASH
FLASH
f
f
f
f
SYS
BUS
SYS
BUS
System and core clock
System and core clock when USB in operation
Bus clock
FlexBus clock
Flash clock
System and core clock
Bus clock
FlexBus clock
Flash clock
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
Port rise and fall time (low drive strength)
Description
Description
2
C signals.
• Slew disabled
• Slew enabled
• Slew disabled
• Slew enabled
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Normal run mode
Preliminary
VLPR mode
TBD
Min.
Min.
100
1.5
20
16
—
—
—
—
—
—
—
—
—
—
—
—
2
Max.
Max.
100
50
50
25
12
36
32
36
—
—
—
—
—
—
2
2
2
1
Bus clock
Bus clock
cycles
cycles
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
Notes
Notes
General
1
2
3
4
2
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