W230-03 Cypress Semiconductor Corp., W230-03 Datasheet - Page 3

• Manufacturer Part Number: W230-03
• Description: Spread Spectrum FTG For Via K7 Chipset
• Manufacturer: Cypress Semiconductor Corp.

Overview
The W230-03 was developed as a single-chip device to meet
the clocking needs of VIA K7 core logic chip sets. In addition
to the typical outputs provided by a standard FTG, the W230-
03 adds a thirteenth output buffer, supporting SDRAM DIMM
modules in conjunction with the chipset.
Cypress’s proprietary spread spectrum frequency synthesis
technique is a feature of the CPU and PCI outputs. When en-
abled, this feature reduces the peak EMI measurements of not
only the output signals and their harmonics, but also of any
other clock signals that are properly synchronized to them.
Functional Description
I/O Pin Operation
Pins 7, 8, 25, 26, and 48 are dual-purpose l/O pins. Upon
power-up these pins act as logic inputs, allowing the determi-
nation of assigned device functions. A short time after power-
up, the logic state of each pin is latched and the pins become
clock outputs. This feature reduces device pin count by com-
bining clock outputs with input select pins.
An external 10-k
the l/O pin and ground or V
latch to “0,” connection to V
Figure 2 show two suggested methods for strapping resistor
connections.
Power-on
Reset
Timer
Power-on
Reset
Timer
W230-03
W230-03
“strapping” resistor is connected between
DD
Output Three-state
Output Three-state
DD
Figure 1. Input Logic Selection Through Resistor Load Option
sets a latch to “1.” Figure 1 and
. Connection to ground sets a
Figure 2. Input Logic Selection Through Jumper Option
Output
Buffer
Output
Buffer
Q
Q
Latch
Latch
Data
Data
PRELIMINARY
D
D
Hold
Output
Low
Hold
Output
Low
(Load Option 1)
(Load Option 0)
3
Upon W230-03 power-up, the first 2 ms of operation is used
for input logic selection. During this period, the five I/O pins (7,
8, 25, 26, 48) are three-stated, allowing the output strapping
resistor on the l/O pins to pull the pins and their associated
capacitive clock load to either a logic HIGH or LOW state. At
the end of the 2-ms period, the established logic “0” or “1”
condition of the l/O pin is latched. Next the output buffer is
enabled converting the l/O pins into operating clock outputs.
The 2-ms timer starts when V
can only be reset by turning V
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of clock outputs is <40
affected by the 10-k strap to ground or V
termination resistor, the output strapping resistor should be
placed as close to the l/O pin as possible in order to keep the
interconnecting trace short. The trace from the resistor to
ground or V
prevent system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, the specified output frequency is delivered on the pin,
assuming that V
full value, output frequency initially may be below target but will
increase to target once V
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
10 k
Jumper Options
10 k
10 k
V
DD
DD
should be kept less than two inches in length to
DD
V
has stabilized. If V
Resistor Value R
DD
R
R
DD
Output Strapping Resistor
Output Strapping Resistor
voltage has stabilized. In either
DD
DD
Series Termination Resistor
Series Termination Resistor
(nominal), which is minimally
reaches 2.0V. The input bits
off and then back on again.
DD
Clock Load
Clock Load
DD
has not yet reached
. As with the series
W230-03