W230-03 Cypress Semiconductor Corp., W230-03 Datasheet - Page 2

• Manufacturer Part Number: W230-03
• Description: Spread Spectrum FTG For Via K7 Chipset
• Manufacturer: Cypress Semiconductor Corp.

Pin Definitions
CPUT0,
CPUC0,
CPU_CS
PCI2:5
PCI1/FS1
PCI0/MODE
PWRDWN#
48MHz/FS2
24_48MHz/
FS3
REF1/FS0
REF0/
CPU_STOP#
SDRAMIN
SDRAM0:12
SCLK
SDATA
X1
X2
VDDQ3
GND
Pin Name
10, 11, 12, 13
20, 18, 17, 40
27, 30, 36, 42
33, 39, 45, 47
1, 6, 14, 19,
3, 9, 16, 22,
34, 32, 31,
29, 28, 21,
38, 37, 35,
Pin No.
43, 44
41
26
25
48
15
24
23
46
8
7
2
4
5
Pin Type
(open-
drain)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
P
G
I
I
I
I
I
PRELIMINARY
CPU Clock Output 0: CPUT0 and CPUC0 are the differential CPU clock outputs
for the K7 processor.
CPU Clock Output for Chipset: CPU_CS is the push-pull clock output for the
chipset. It has the same phase relationship as CPUT0.
PCI Clock Outputs 2 through 5: These four PCI clock outputs are controlled by
the PWRDWN# control pin. Frequency is set by FS0:3 inputs or through serial
input interface, see Tables 2 and 6 for details. Output voltage swing is controlled
by voltage applied to VDDQ3.
Fixed PCI Clock Output/Frequency Select 1: As an output, frequency is set by
FS0:3 inputs or through serial input interface. This output is controlled by the
PWRDWN# input. This pin also serves as a power-on strap option to determine
device operating frequency as described in Table 2.
Fixed PCI Clock Output/Mode: As an output, frequency is set by the FS0:3 inputs
or through serial input interface, see Tables 2 and 6. This output is controlled by
the PWRDWN# input. This pin also serves as a power-on strap option to determine
the function of pin 2, see Table 1 for details.
PWRDWN# Input: LVTTL-compatible input that places the device in power-down
mode when held LOW. In power-down mode, CPUC0 will be three-stated and all
the other output clocks will be driven LOW.
48-MHz Output/Frequency Select 2: 48 MHz is provided in normal operation. In
standard PC systems, this output can be used as the reference for the Universal
Serial Bus host controller. This pin also serves as a power on strap option to
determine device operating frequency as described in Table 2.
24_48-MHz Output/Frequency Select 3: In standard PC systems, this output can
be used as the clock input for a Super I/O chip. The output frequency is controlled
by Configuration Byte 3 bit[6]. The default output frequency is 48 MHz. This pin
also serves as a power-on strap option to determine device operating frequency
as described in Table 2.
Reference Clock Output 1/Frequency Select 2: 3.3V 14.318-MHz output clock.
This pin also serves as a power-on strap option to determine device operating
frequency as described in Table 2. Upon power-up, FS0 input will be latched which
will set clock frequencies as described in Table 2.
Reference Clock Output 0 or CPU_STOP# Input Pin: Function is determined
by the MODE pin. When CPU_STOP# input is asserted LOW, it will drive CPUT0
and CPU_CS to logic 0, and it will three-state CPUC0. When this pin is configured
as an output, this pin becomes a 3.3V 14.318-MHz output clock.
Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs
(SDRAM0:12).
Buffered Outputs: These thirteen dedicated outputs provide copies of the signal
provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deac-
tivated when PWRDWN# input is set LOW.
Clock pin for I
Data pin for I
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs,
PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output. Connect
to 3.3V supply
Ground Connections: Connect all ground pins to the common system ground
plane.
2
2
C circuitry.
C circuitry.
2
Pin Description
W230-03