W230-03 Cypress Semiconductor Corp., W230-03 Datasheet

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W230-03

Manufacturer Part Number
W230-03
Description
Spread Spectrum FTG For Via K7 Chipset
Manufacturer
Cypress Semiconductor Corp.
Datasheet

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W230-03H
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Features
Key Specifications
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
V
SDRAMIN to SDRAM0:12 Delay: ..........................3.7 ns typ.
Table 1. Mode Input Table
I
Cypress Semiconductor Corporation
2
• Maximized EMI Suppression using Cypress’s Spread
• Single-chip system frequency synthesizer for VIA K7
• Two copies of CPU output
• Six copies of PCI output
• One 48-MHz output for USB
• One 24-MHz or 48-MHz output for SIO
• Two buffered reference outputs
• Thirteen SDRAM outputs provide support for 3 DIMMs
• Supports frequencies up to 200 MHz
• I
• Power management control inputs
• Available in 48-pin SSOP
Block Diagram
C is a trademark of Phillips Corporation.
DDQ3
Spectrum technology
chipset
2
PWRDWN#
C™ interface for programming
SDRAMIN
: .................................................................... 3.3V±5%
SDATA
SCLK
Mode
X1
X2
0
1
PLL 1
Logic
I
2
PLL2
C
XTAL
OSC
÷2,3,4
I/O Pin
Control
PLL Ref Freq
Control
Clock
Stop
÷2
CPU_STOP#
REF0
Pin 2
13
VDDQ3
48MHz/FS2
VDDQ3
VDDQ3
REF0/(CPU_STOP#)
REF1/FS0
CPU_CS
PCI0/MODE
PCI1/FS1
PCI2
PCI3
PCI4
PCI5
CPUT0
CPUC0
24_48MHz/FS3
VDDQ3
SDRAM0:12
Spread Spectrum FTG for VIA K7 Chipset
3901 North First Street
PRELIMINARY
Table 2. Pin Selectable Frequency
FS3 FS2 FS1 FS0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Input Address
Note:
Pin Configuration
REF0/(CPU_STOP#)
1.
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
Internal pull-up resistors should not be relied upon for setting I/O
I
2
PCI0/MODE
C
San Jose
PCI1/FS1*
SDRAM11
SDRAM10
SDRAMIN
{
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
SDRAM9
SDRAM8
VDDQ3
VDDQ3
VDDQ3
VDDQ3
SDATA
SCLK
GND
GND
PCI2
PCI3
PCI4
PCI5
GND
GND
X1
X2
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CPU_CS
CPUT0
(MHz)
100.0
100.0
100.0
133.3
133.3
133.3
102.0
104.0
106.0
107.0
108.0
109.0
110.0
111.0
112.0
[1]
95.0
CA 95134
September 7, 2000, Rev. **
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PCI 0:5
(MHz)
33.3
33.3
33.3
31.7
33.3
33.3
33.3
34.0
34.6
35.3
35.6
36.0
36.3
36.6
37.0
37.3
REF1/FS0*
GND
CPU_CS
GND
CPUC0
CPUT0
VDDQ3
PWRDWN#*
SDRAM12
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
VDDQ3
48MHz/FS2*
24_48MHz/FS3^
W230-03
408-943-2600
Spectrum
Spread
–0.5%
±0.5%
–0.5%
±0.5%
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF

Related parts for W230-03

W230-03 Summary of contents

Page 1

... HIGH. Pin function with parentheses determined by MODE pin 24_48MHz/FS3 resistor strapping. Unlike other I/O pins, input FS3 has an internal VDDQ3 pull-down resistor. SDRAM0:12 13 • 3901 North First Street • San Jose W230-03 CPU_CS CPUT0 PCI 0:5 Spread (MHz) (MHz) Spectrum 1 1 100.0 33.3 – ...

Page 2

... Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output. Connect to 3.3V supply Ground Connections: Connect all ground pins to the common system ground plane. 2 W230-03 ...

Page 3

... Timer Figure 2. Input Logic Selection Through Jumper Option PRELIMINARY Upon W230-03 power-up, the first operation is used for input logic selection. During this period, the five I/O pins (7, 8, 25, 26, 48) are three-stated, allowing the output strapping resistor on the l/O pins to pull the pins and their associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic “ ...

Page 4

... Spread Spectrum clocking is activated or deactivated by se- lecting the appropriate values for bits 1–0 in data byte 0 of the data stream. Refer to Table 6 for more details. Typical Clo ck Spread Spectrum Enabled Figure 4. Typical Modulation Profile 4 W230-03 EMI Reduction Non- Spread Speactrum Frequency Span (MHz) Down Spread ...

Page 5

... No user application. Register bit must be writ- ten as 0. Byte Description Commands the W230-03 to accept the bits in Data Bytes 0–6 for internal register configuration. Since other devices may exist on the same com- mon serial data bus necessary to have a specific slave address for each potential receiver ...

Page 6

... Control Function 0 -- Hardware Normal -- -- -- -- -- -- -- -- -- Low -- Low Low Low Low Low -- 24-MHz Low Low -- Low 6 W230-03 Bit Control 1 Default -- 0 See Table 6 0 See Table 6 0 See Table 6 0 Software 0 See Table 6 1 See Table 6 0 Three-stated ...

Page 7

... Data Byte (Reserved (Reserved (Reserved (Reserved (Reserved (Reserved (Reserved (Reserved) PRELIMINARY Control Function Low Low -- -- -- -- -- -- -- -- -- -- -- -- -- -- Low Low -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 7 W230-03 Bit Control 0 1 Default Active Active -- -- -- -- -- -- -- -- -- -- -- -- -- -- Active Active -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ...

Page 8

... W230-03 Output Frequency PCI Spread Spectrum 33.3 –0.5% 33.3 OFF 33.3 ±0.5% 31.7 OFF 33.3 –0.5% 33.3 OFF 33.3 ±0.5% 34.0 OFF 34.6 OFF 35.3 OFF 35.6 OFF 36.0 OFF 36.3 OFF 36.6 OFF 37 ...

Page 9

... All clock outputs loaded with 6" 60 transmission lines with 20-pF capacitors. 3. W230-03 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device. PRELIMINARY above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability ...

Page 10

... DD 5. The W230-03 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). ...

Page 11

... Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to fre- quency stabilization. Average value during switching transition. Used for determining series termination value. 11 W230-03 Min. Typ. Max. Unit ...

Page 12

... Average value during switching transition. Used for determining series termination value. VDD + V1 3 Length = 5” Length = 5” Figure 5. K7 Open Drain Clock Driver Test Circuit Package Name H 48-pin SSOP (300 mils) 12 W230-03 Min. Typ. Max. 24.004 +167 57/34 0 Length = 3 ” ...

Page 13

... Ceramic C4 = 0.005 0. =VIA to respective supply plane layer 13 W230- ...

Page 14

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY W230-03 ...

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