zpsd211r STMicroelectronics, zpsd211r Datasheet - Page 22

• Manufacturer Part Number: zpsd211r
• Description: Low Cost Field Programmable Microcontroller Peripherals
• Manufacturer: STMicroelectronics

12.
Control Signals
(Cont.)
Figure 8. The Required Reset Cycle for ZPSD211RV Devices Only.
Table 8A. External PSD Signal States During and Just After Reset
NOTE: 1. Signal is valid immediately after reset for non-V devices. ZPSD211RV devices need an additional
Table 8B. Internal PSD Signal States During and Just After Reset
NOTE: N/A = Not Applicable
AD0/A0-
AD15/A15
Port Pins
PA0-PA7
Port Pins
PB0-PB7
Port Pins
PC0-PC2
PAD A and PAD B
All registers in CSIOPORT
address space, including:
Port
Direction
Data
PMR (turbo bit, ZPSD only)
V
V
IL
IH
500 nsec after reset before signal is valid.
Component
All
MCU I/O
Latched Address Out
MCU I/O
Chip Select Outputs,
CS0-CS7, CMOS
Chip Select Outputs,
CS0-CS7, Open Drain
Address or Logic Inputs, A16-A18
Chip Select Outputs,
CS8-CS10, CMOS
Configured Mode of Operation
RESET LOW
500 ns
Internal Signal
CSIOPORT,
CS0-CS10
ES0-ES7
PSD211R,
ZPSD211R
ZPSD211RV
PSD211R,
ZPSD211R
ZPSD211RV
PSD211R,
ZPSD211R
ZPSD211RV
PSD211R,
ZPSD211R
ZPSD211RV
N/A
RESET HIGH
500 ns
Logic 0 in all bit of
Logic 1 (inactive) Per CS Equations
Logic 0 (inactive)
Internal Signal
During Reset
State During
Signal State
all registers
Input (Hi-Z)
Input (Hi-Z)
Input (Hi-Z)
Input (Hi-Z
Logic 0
Logic 1
Logic 1
Reset
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
ZPSD211R(V)
IS OPERATIONAL
Signal State Just
Per CS equations
Per CS equations
Per CS equations
Per CS equations
Per CS equations
Per CS equations
changed by MCU
MCU address
MCU address
MCU address
After Reset
Power-Down
Per equations
internal signal
Signal State
and/or data
Input (Hi-Z)
Input (Hi-Z)
Input (Hi-Z)
Logic 0 until
PSD211R Family
(Note 1)
Internal
for each
During
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