zpsd211r STMicroelectronics, zpsd211r Datasheet - Page 17

• Manufacturer Part Number: zpsd211r
• Description: Low Cost Field Programmable Microcontroller Peripherals
• Manufacturer: STMicroelectronics

10.0
I/O Port
Functions
(Cont.)
14
PSD211R Family
Figure 6. Port B Pin Structure
10.3 Port B (PB0-PB7)
MCU I/O Mode
The default configuration of Port B is MCU I/O. In this mode, every pin can be set
(at run-time) as an input or output by writing to the respective pin’s direction flip-flop (DIR
FF, Figure 6). As an output, the pin level can be controlled by writing to the respective pin’s
data flip-flop (DFF, Figure 6). The Pin Register can be read to determine logic level of the
pin. The contents of the Pin Register indicate the true state of the PSD driving the pin
through the DFF or an external source driving the pin.
Chip Select Output
Alternatively, each bit of Port B can be configured to provide a chip-select output signal
from PAD B. PB0-PB7 can provide CS0-CS7, respectively. The functionality of these pins
is not limited to chip selects only; they can be used for generic combinatorial logic as well.
Each of the CS0-CS3 signals is comprised of four product terms, and each of the CS4-CS7
signals is comprised of two product terms.
The control registers of Port B are located in CSIOPORT space; see Table 5. Each pin of
Port B can be individually configured. The following table summarizes what the control
registers (in CSIOPORT space) for Port B do:
NOTE: 1. Default value is the value after reset.
Port B Pin Register
Port B Direction Register
Port B Data Register
Register Name
N
R
N
C
O
U
T
E
A
L
S
T
U
C
S
I
B
S
0
7
•
•
•
RESET
N
R
N
D
A
T
A
D
D
T
E
A
L
B
U
S
8
1
5
•
•
•
I
WRITE DATA
WRITE DIR
READ DATA
READ DIR
CK
CK
D
D
R
R
DFF
DIR
FF
Sampled logic level
Data in DFF = ‘0’
Pin is configured
at pin = ‘0’
0 Value
as input
CSn
MCU
OUT
I/O
MUX
READ PIN
CONTROL
Sampled logic level
Data in DFF = ‘1’
Pin is configured
at pin = ‘1’
as output
1 Value
ENABLE
PORT B PIN
Default
Value
(Note 1)
X
0
0