zpsd211r STMicroelectronics, zpsd211r Datasheet - Page 16

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zpsd211r

Manufacturer Part Number
zpsd211r
Description
Low Cost Field Programmable Microcontroller Peripherals
Manufacturer
STMicroelectronics
Datasheet

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10.0
I/O Port
Functions
(Cont.)
10.2 Port A (PA0-PA7)
Latched Address Output Mode
Alternatively, any bit(s) of Port A can be configured to output a low-order demultiplexed
address bus bit. The address is provided by the internal PSD address latch, which latches
the address on the trailing edge of ALE/AS. Port A then outputs the desired demultiplexed
address bits. This feature can eliminate the need for an external latch (for example:
74LS373) if you have devices that require low-order latched address bits. Although any pin
of Port A may output an address signal, the pin is position-dependent. In other words, pin
PA0 of Port A may only pass A0, PA1 only A1, and so on.
The control registers of Port A are located in CSIOPORT space; see Table 5. Each pin of
Port A can be individually configured. The following table summarizes what the control
registers (in CSIOPORT space) for Port A do:
Figure 5. Port A Pin Structure
NOTE: 1. Default value is the value after reset.
Port A Pin Register
Port A Direction Register
Port A Data Register
Register Name
RESET
N
E
R
N
A
A
D
D
R
D
A
A
B
U
S
A
D
A
D
T
L
T
0
7
I
/
/
WRITE DATA
WRITE DIR
ALE
READ DATA
(Cont.)
READ DIR
CK
CK
G
D
D
D
LATCH
DFF
DIR
FF
R
R
R
Sampled logic level
Data in DFF = ‘0’
Pin is configured
LATCHED
at pin = ‘0’
ADDR
0 Value
OUT
as input
MCU
OUT
I/O
MUX
READ PIN
CONTROL
Sampled logic level
Data in DFF = ‘1’
Pin is configured
at pin = ‘1’
ENABLE
as output
1 Value
PORT A PIN
Default
PSD211R
Value
(Note 1)
X
0
0
13

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