isd-t360sb ETC-unknow, isd-t360sb Datasheet - Page 99
![no-image](/images/no-image-200.jpg)
isd-t360sb
Manufacturer Part Number
isd-t360sb
Description
Manufacturer
ETC-unknow
Datasheet
1.ISD-T360SB.pdf
(112 pages)
- Current page: 99 of 112
- Download datasheet (2Mb)
2—SOFTWARE
ISD
68
69
79
Index
Index
Frame Synch Delay:
CFSD
Data Valid Delay:
CFET
PLL_Configuration:
PLL_MODE
Parameter Name
Parameter Name
Table 2-11: TUNABLE PARAMETERS: Codec Support (Samples)
Table 2-12: TUNABLE PARAMETERS: Clocking
The delay of Frame Synch 1 (CFS1) from Frame Synch 0
(CFS0).
Legal values: 0 to 255
The delay between Frame Synch 0 (CFS0) to end of valid
data of all channels.
Legal values: 0 to 255
Controls the internal clock PLL multiplication factor, which
generates the master system clock. The default value (0)
allows using external crystal (or oscillator) of 4.096Mhz.
Setting this value to 1 allows using external crystal (or
oscillator) of 65.536Mhz.
Legal values: 0, 1
Description
Description
ISD-T360SB
16
25
0
Default
Default
2-63
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