w83977tf Winbond Electronics Corp America, w83977tf Datasheet - Page 53

• Manufacturer Part Number: w83977tf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read
Bit 1: TDSR. This bit indicates that the DSR pin has changed state after HSR was read by the CPU.
Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read.
3.2.5 UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if the
TABLE 3-3 FIFO TRIGGER LEVEL
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to a
Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to a
Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before
BIT 7
by the CPU.
interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver
FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.
UFR bit 0 = 1.
logical 0 by itself after being set to a logical 1.
logical 0 by itself after being set to a logical 1.
other bits of UFR are programmed.
0
0
1
1
BIT 6
7
0
1
0
1
6
5
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
4
3
2
1
- 45 -
01
04
08
14
0
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Publication Release Date: March 1998
W83977TF
PRELIMINARY
Revision 0.62