w83977tf Winbond Electronics Corp America, w83977tf Datasheet - Page 103

• Manufacturer Part Number: w83977tf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

Register
GP0STS1
GP0STS2
GP1STS1
GP1STS2
GP0EN1
GP0EN2
GP1EN1
GP1EN2
Table 9-2: Bit Map of GPE Register Block
10. SERIAL IRQ
W83977TF supports a serial IRQ scheme. This allow a signal line to be used to report the legacy ISA
interrupt rerquests. Because more than one device may need to share the signal serial IRQ signal
line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is
transfered on the IRQSER signal, one cycle consisting of three frames types: a start frame, several
IRQ/Data frame, and one Stop frame.
Specification for PCI System, Version 6.0.
Timing Diagrams For IRQSER Cycle
Start Frame timing with source sampled a low pulse on IRQ1
PCICLK
IRQSER
Drive Source
1. Start Frame pulse can be 4-8 clocks wide.
<CR62,63>
<CR62,63>
+1H
<CR62,63>
+2H
<CR62,63>
+3H
<CR64,65>
<CR64,65>
+1H
<CR64,65>
+2H
<CR64,65>
+3H
Address
H=Host Control
Reset Value
Power-On
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
SL
or
H
IRQ1
SL=Slave Control
START
H
Host Controller
D7
START FRAME
0
0
0
0
0
0
0
0
1
D6
0
0
0
0
0
0
0
0
R
MOUSCISTS
MOUSCIEN
R=Recovery
D5
0
0
0
0
0
0
T
The serial interrupt scheme adheres to the Serial IRQ
-93 -
S
None
IRQ0 FRAME
KBCSCISTS
KBCSCIEN
R
D4
0
0
0
0
0
0
T=Turn-around
T
PRTSCISTS
PRTSCIEN
S
IRQ1 FRAME
IRQ1
D3
0
0
0
0
0
0
Publication Release Date:March 1998
R
T
FDCSCISTS
FDCSCIEN
S=Sample
W83977TF
D2
S
0
0
0
0
0
0
PRELIMINARY
None
IRQ2 FRAME
R
URASCISTS
BM_CNTRL
URASCIEN
TMR_ON
T
Revision 0.62
D1
0
0
0
0
URBSCISTS
URBSCIEN
BIOS_STS
BIOS_RLS
BIOS_EN
D0
0
0
0