w83977tf Winbond Electronics Corp America, w83977tf Datasheet - Page 132

• Manufacturer Part Number: w83977tf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

CRF5 (Default 0x00)
CRF6 (Default 0x00)
Bit 1: URAIDLEN.
Bit 0: URBIDLEN.
Bit 7 - 4: Reserved. Return zero when read.
Bit 3 - 0: Enable bits of the
These bits enable the generation of an
input to the device. These 4 bits control the printer port, FDC, UART A, and UART B SMI logics
respectively.
Bit 3: PRTTRAPEN.
Bit 2: FDCTRAPEN.
Bit 1: URATRAPEN.
Bit 0: URBTRAPEN.
Bit 7 - 6: Reserved. Return zero when read.
Bit 5 - 0: Enable bits of the
These bits enable the generation of an
control the printer port, FDC, UART A, and UART B
output for the IRQs is as follows:
SMI
logic output = (URBIRQEN and URBIRQSTS) or (URAIRQEN and URAIRQSTS) or
= 0
= 1
= 0
= 1
= 0
= 1
= 0
= 1
= 0
= 1
= 0
= 1
disable the generation of an
enable the generation of an
disable the generation of an
enable the generation of an
disable the generation of an
enable the generation of an
disable the generation of an
enable the generation of an
disable the generation of an
enable the generation of an
disable the generation of an
enable the generation of an
(FDCIRQEN and FDCIRQSTS) or (PRTIRQEN and PRTIRQSTS)
(KBCIRQEN and KBCIRQSTS) or (MOUIRQEN and MOUIRQSTS)
SMI
SMI
generation due to device's trap.
generation due to the device's IRQ.
-121-
SMI
SMI
SMI
SMI
SMI
SMI
SMI
SMI
SMI
SMI
SMI
SMI
SMI
SMI
interrupt due to any IRQ of the devices. These 4 bits
interrupt due to UART A's idleness.
interrupt due to UART B's idleness.
interrupt due to printer port's trap.
interrupt due to FDC's trap.
interrupt due to UART A's trap.
interrupt due to UART B's trap.
interrupt due to any I/O access, IRQ, and external
interrupt due to UART A's idleness.
interrupt due to UART B's idleness.
interrupt due to printer port's trap.
interrupt due to FDC's trap.
interrupt due to UART A's trap.
interrupt due to UART B's trap.
SMI
logics respectively. The
Publication Release Date: March 1998
W83977TF
PRELIMINARY
Revision 0.62
SMI
logic