w83977tf Winbond Electronics Corp America, w83977tf Datasheet - Page 131

• Manufacturer Part Number: w83977tf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

CRF3 (Default 0x00)
by their source device and is cleared by writing a 1. Writing a 0 has no effect.
CRF4 (Default 0x00)
Bit 2: FDCTRAPSTS. FDC trap status.
Bit 1: URATRAPSTS. UART A trap status.
Bit 0: URBTRAPSTS. UART B trap status.
Bit 7 - 6: Reserved. Return zero when read.
Bit 5 - 0: Device's IRQ status.
These bits indicate the IRQ status of the individual device. The device's IRQ status
Bit 5: MOUIRQSTS. MOUSE IRQ status.
Bit 4: KBCIRQSTS. KBC IRQ status.
Bit 3: PRTIRQSTS. printer port IRQ status.
Bit 2: FDCIRQSTS. FDC IRQ status.
Bit 1: URAIRQSTS. UART A IRQ status.
Bit 0: URBIRQSTS. UART B IRQ status.
Bit 7 - 4: Reserved. Return zero when read.
Bit 3 - 0: Enable bits of the
These bits enable the generation of an
timer. These 4 bits control the printer port, FDC, UART A, and UART B
Bit 3: PRTIDLEN.
Bit 2: FDCIDLEN.
= 0
= 1
= 0
= 1
= 0
= 1
= 0
= 1
= 0
= 1
FDC is now in the sleeping state.
FDC is now in the working state due to any FDC access, any IRQ, any DMA
acknowledge, and any enabling of the motor enable bits in the DOR register.
UART A is now in the sleeping state.
UART A is now in the working state due to any UART A access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins transmitting a
start bit, and any transition on MODEM control input lines.
UART B is now in the sleeping state.
UART B is now in the working state due to any UART B access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins transmitting
a start bit, and any transition on MODEM control input lines.
disable the generation of an
enable the generation of an
disable the generation of an
enable the generation of an
SMI
generation due to the device's idleness.
-120-
SMI
SMI
SMI
SMI
SMI
interrupt due to printer port's idleness.
interrupt due to FDC's idleness.
interrupt due to printer port's idleness.
interrupt due to FDC's idleness.
interrupt due to the expiration of the device's idle
Publication Release Date: March 1998
SMI
W83977TF
PRELIMINARY
logics respectively.
Revision 0.62
bit is set