w83977atg Winbond Electronics Corp America, w83977atg Datasheet - Page 78

• Manufacturer Part Number: w83977atg
• Description: W83877tf Plus Kbc, Gp I/o, Wake-up, Fir, Cir, Pb-free
• Manufacturer: Winbond Electronics Corp America

Bit 7~5
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
7.7.3
Writing this register selects Register Set. Reading this register returns ECH.
7.7.4
Bit 7:
Bit 6:
Default Value
Reset Value
IRCFG1
REG.
SSR
REG.
Set5.Reg3 - Sets Select Register (SSR)
Set5.Reg4 - Infrared Configure Register 1 (IRCFG1)
FSF_TH
FC_MD2 - Flow Control Mode
When flow control is enforced, these bits will be loaded into AD_MD2~0 of advanced HSR
(Handshake Status Register). These three bits are defined as same as AD_MD2~0.
Reserved, write 0.
FC_DSW - Flow Control DMA Channel Swap
A write to 1 allows user to swap DMA channel for transmitter or receiver when flow control is
enforced.
EN_FD - Enable Flow DMA Control
A write to 1 enables UART to use DMA channel when flow control is enforced.
EN_BRFC - Enable Baud Rate Flow Control
A write to 1 enables FC_BLL/FC_BHL (Flow Control Baud Rate Divider Latch, in Set5.Reg1~0) to
be loaded into advanced baud rate divisor latch (ADBLL/ADBHL, in Set2.Reg1~0).
EN_FC - Enable Flow Control
A write to 1 enables flow control function and bit 7~1 of this register.
Reserved, write 0.
FSF_TH - Frame Status FIFO Threshold
Set this bit to determine the frame status FIFO threshold level and to generate the FSF_I.
The threshold level values are defined as follows.
0
1
BIT 7
SSR7
BIT 7
1
FC_DSW
0
-
0
1
FSF_TH
BIT 6
SSR6
BIT 6
1
0
SSR5
BIT 5
FEND_M
1
BIT 5
0
Next Mode After Flow Control Occurred
- 70 -
STATUS FIFO THRESHOLD LEVEL
SSR4
BIT 4
0
AUX_RX
BIT 4
Transmitter Channel
W83977ATF/W83977ATG
0
Receiver Channel
BIT 3
SSR3
1
BIT 3
0
-
2
4
BIT 2
SSR2
BIT 2
1
0
-
IRHSSL
SRR1
BIT 1
BIT 1
0
0
IR_FULL
SRR0
BIT 0
BIT 0
0
0