w83977atg Winbond Electronics Corp America, w83977atg Datasheet - Page 14

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w83977atg

Manufacturer Part Number
w83977atg
Description
W83877tf Plus Kbc, Gp I/o, Wake-up, Fir, Cir, Pb-free
Manufacturer
Winbond Electronics Corp America
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
w83977atg-AW
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
4. PIN DESCRIPTION
Note: Please refer to Section 12.2 DC CHARACTERISTICS for details.
I/O
I/O
I/O
I/O
I/O
I/O
I/OD
pull-up resistor
I/O
OUT
OUT
OD
OD
IN
IN
IN
IN
IN
IN
4.1
A0−A10
A11-A14
A15
D0−D5
D6−D7
AEN
IOCHRDY
MR
IOR
IOW
t
c
cu
cs
ts
tsu
6t
8t
8
12t
12
16u
24t
SYMBOL
12
24
16u
8t
12t
Host Interface
- TTL level bi-directional pin with 6 mA source-sink capability
- TTL level bi-directional pin with 8 mA source-sink capability
- CMOS level bi-directional pin with 8 mA source-sink capability
- TTL level bi-directional pin with 12 mA source-sink capability
- CMOS level bi-directional pin with 12 mA source-sink capability
- CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor
- TTL level bi-directional pin with 24 mA source-sink capability
- TTL level output pin with 8 mA source-sink capability
- TTL level output pin with 12 mA source-sink capability
- Open-drain output pin with 12 mA sink capability
- Open-drain output pin with 24 mA sink capability
- TTL level input pin
- CMOS level input pin
- CMOS level input pin with internal pull-up resitor
- CMOS level Schmitt-triggered input pin
- TTL level Schmitt-triggered input pin
- TTL level Schmitt-triggered input pin with internal pull-up resistor
- CMOS level bi-directional pin open drain output with 16 mA sink capability with internal
74-84
86-89
109-
116-
PIN
114
117
105
106
107
108
118
91
OD24
I/O
I/O
INts
IN
IN
IN
I/O
IN
IN
IN
12t
12t
ts
ts
ts
t
t
t
System address bus bits 0-10.
System address bus bits 11-14.
System address bus bit 15.
System data bus bits 0-5.
System data bus bits 6-7.
CPU I/O read signal.
CPU I/O write signal.
System address bus enable.
In EPP Mode, this pin is the IO Channel Ready output to extend the host
read/write cycle.
Master Reset; Active high; MR is low during normal operations.
- 6 -
W83977ATF/W83977ATG
FUNCTION

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