w83977atg Winbond Electronics Corp America, w83977atg Datasheet - Page 62

• Manufacturer Part Number: w83977atg
• Description: W83877tf Plus Kbc, Gp I/o, Wake-up, Fir, Cir, Pb-free
• Manufacturer: Winbond Electronics Corp America

TABLE: INTERRUPT CONTROL FUNCTION
** Bit 3 of ISR is enabled when bit 0 of UFR is a logical 1.
Advanced IR:
Bit 3:
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit
3
0
0
0
1
0
Bit
2
0
1
1
1
0
MIR, FIR modes:
Advanced SIR/ASK-IR, Remote IR modes: Not used.
MIR, FIR, Remote IR Modes:
ISR
TMR_I - Timer Interrupt.
Set to 1 when timer counts to logical 0. This bit is valid when: (1) the timer registers are
defined in Set4.Reg0 and Set4.Reg1; (2) EN_TMR(Enable Timer, in Set4.Reg2.Bit0) is
set to 1; (3) ENTMR_I (Enable Timer Interrupt, in Set0.Reg1.Bit7) is set to 1.
FSF_I - Frame Status FIFO Interrupt.
Set to 1 when Frame Status FIFO is equal or larger than the threshold level or Frame
Status FIFO time-out occurs.
threshold level.
TXTH_I - Transmitter Threshold Interrupt.
Set to 1 if the TBR (Transmitter Buffer Register) FIFO is below the threshold level.
Cleared to 0 if the TBR (Transmitter Buffer Register) FIFO is above the threshold level.
DMA_I - DMA Interrupt.
Set to 1 if the DMA controller 8237A sends a TC (Terminal Count) to I/O device which
might be a Transmitter TC or a Receiver TC. Cleared to 0 when this register is read.
HS_I - Handshake Status Interrupt.
Set to 1 when the Handshake Status Register has a toggle. Cleared to 0 when
Handshake Status Register (HSR) is read. Note that in all IR modes including SIR, ASK-
IR, MIR, FIR, and Remote Control IR, this bit defaults to be inactive unless IR Handshake
Status Enable (IRHS_EN) is set to 1.
Bit
1
0
1
0
0
1
Bit
0
0
0
0
0
1
First
Second
Second
Third
Interrupt
priority
-
IR Receive
Status
RBR Data
Ready
FIFO Data
Time-out
TBR
Empty
Interrupt
Type
-
Cleared to 0 when Frame Status FIFO is below the
INTERRUPT SET AND FUNCTION
- 54 -
No Interrupt pending
1. OER = 1
3. NSER = 1 4. SBD = 1
1. RBR data ready
2. FIFO interrupt active level
Data present in RX FIFO for
4 characters period of time
since last access of RX
FIFO.
TBR empty
reached
W83977ATF/W83977ATG
Interrupt Source
2. PBER =1
Read USR
1. Read RBR
2. Read RBR until FIFO
data under active level
Read RBR
1. Write data into TBR
2. Read ISR (if priority
is third)
Clear Interrupt
-