w83977atg Winbond Electronics Corp America, w83977atg Datasheet - Page 54

• Manufacturer Part Number: w83977atg
• Description: W83877tf Plus Kbc, Gp I/o, Wake-up, Fir, Cir, Pb-free
• Manufacturer: Winbond Electronics Corp America

Bit 2: FERI. This bit indicates that the RI pin has changed from low to high state after HSR was read
Bit 1: TDSR. This bit indicates that the DSR pin has changed state after HSR was read by the CPU.
Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read.
6.2.5
This register is used to control the FIFO functions of the UART.
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
TABLE 6-3 FIFO TRIGGER LEVEL
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to
Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to
Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before
BIT 7
by the CPU.
the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.
UFR bit 0 = 1.
a logical 0 by itself after being set to a logical 1.
a logical 0 by itself after being set to a logical 1.
other bits of UFR are programmed.
UART FIFO Control Register (UFR) (Write only)
0
0
1
1
7
BIT 6
6
0
1
0
1
5
4
3
2
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
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1
0
W83977ATF/W83977ATG
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
01
04
08
14