pdi1394p25 NXP Semiconductors, pdi1394p25 Datasheet - Page 7

• Manufacturer Part Number: pdi1394p25
• Description: 1-port 400 Mbps Physical Layer Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
2001 Sep 06
PLLGND
PLLV
RESET
R0
R1
SYSCLK
TEST0
TESTM
TPA0+
TPA0–
TPB0+
TPB0–
TPBIAS0
XI
XO
1-port 400 Mbps physical layer interface
Name
DD
CMOS 5 V tol
Pin Type
Supply
Supply
CMOS
CMOS
CMOS
Crystal
Cable
Cable
Cable
Cable
Cable
Bias
Numbers
57, 58
56
53
40
41
2
29
27
37
36
35
34
38
59
60
LQFP
Pin
Numbers
D3, E1
D1, D4
C1
D5
A4
H2
C8
D7
B5
B6
C6
A7
A6
E2
E3
LFBGA
Ball
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
—
O
I
I
I
PLL circuit ground terminals. These terminals should be tied together to
the low impedance circuit board ground plane.
PLL circuit power terminals. A combination of high frequency decoupling
capacitors near each terminal are suggested, such as paralleled 0.1 F
and 0.001 F. These supply terminals are separated from DV
AV
tied at a low impedance point on the circuit board.
Logic reset input. Asserting this terminal low resets the internal logic. An
internal pull-up resistor to V
delay capacitor is required for proper power-up operation. For more
information, refer to Section 17.2. This input is otherwise a standard
Schmitt logic input, and can also be driven by an open-drain type driver.
Current setting resistor pins These pins are connected to an external
resistance to set the internal operating currents and cable driver output
currents. A resistance of 6.34 k
1394–1995 Std. output voltage limits.
System clock output. Provides a 49.152 MHz clock signal, synchronized
with data transfers, to the LLC.
Test control input. This input is used in manufacturing tests of the
PDI1394P25. For normal use, this terminal should be tied to GND.
Test control input. This input is used in manufacturing tests of the
PDI1394P25. For normal use, this input may be tied to V
compatibility with other vendors’ pin-compatible PHY chips) or to PHY
GND (when a PDI1394P25 is an alternate device).
Twisted-pair cable A differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept
matched and as short as possible to the external load resistors and to
the cable connector.
Twisted-pair cable B differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept
matched and as short as possible to the external load resistors and to
the cable connector.
Twisted-pair bias output. This provides the 1.86 V nominal bias voltage
needed for proper operation of the twisted-pair cable drivers and
receivers, and for signaling to the remote nodes that there is an active
cable connection. These terminals must be decoupled with a
0.3 F–1 F capacitor to ground.
Crystal oscillator inputs. These terminals connect to a 24.576 MHz
parallel resonant fundamental mode crystal. The optimum values for the
external shunt capacitors are dependent on the specifications of the
crystal used. Can also be driven by an external clock generator (leave
XO unconnected in this case and start supplying the external clock
before resetting the PDI1394P25). For more information, refer to
Section 17.5
7
DD
internal to the device to provide noise isolation. They should be
g
g
DD
Description
is provided so only an external
1% is required to meet the IEEE
g
g
PDI1394P25
DD
Preliminary data
(for
DD
and