pdi1394p25 NXP Semiconductors, pdi1394p25 Datasheet - Page 37

• Manufacturer Part Number: pdi1394p25
• Description: 1-port 400 Mbps Physical Layer Interface
• Manufacturer: NXP Semiconductors

1. Normal operation. Interface is operating normally, with LPS
2. LPS deasserted. The LLC deasserts the LPS signal and, within 1
Philips Semiconductors
The sequence of events for disabling the PHY-LLC interface when it
is in the differentiated mode of operation (ISO terminal is low) is as
follows:
2001 Sep 06
1-port 400 Mbps physical layer interface
active, SYSCLK active, status and packet data reception and
transmission via the CTL and D lines, and request activity via the
LREQ line.
ms, terminates any request or interface bus activity, and places
its LREQ, CTL, and D outputs into a high-impedance state (the
LLC should terminate any output signal activity such that signals
end in a logic 0 state).
CTL0, CTL1
SYSCLK
D0 – D7
LREQ
LPS
ISO
(high)
(a)
Figure 23. Interface Disable, ISO High
(b)
T
LPS_RESET
37
3. Interface reset. After T
4. Interface disabled. If the LPS signal remain inactive for
LPS is inactive, terminates any interface bus activity, and places
its CTL and D outputs into a high-impedance state (the PHY will
terminate any output signal activity such that signals end in a
logic 0 state). The PHY-LLC interface is now in the reset state.
T
placing the SYSCLK output into a high-impedance state. The
PHY-LLC interface is now in the disabled state.
T
LPS_DISABLE
LPS_DISABLE
(c)
time, the PHY terminates SYSCLK activity by
LPS_RESET
time, the PHY determines that
PDI1394P25
(d)
Preliminary data
SV01813