pxb4219 Infineon Technologies Corporation, pxb4219 Datasheet - Page 74
pxb4219
Manufacturer Part Number
pxb4219
Description
Iwe8 Interworking Element For 8 E1/t1 Lines
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PXB4219.pdf
(290 pages)
- Current page: 74 of 290
- Download datasheet (4Mb)
Transmit
Receive
Figure 19
4.5.1
In transmit direction the ICRC generates RTS values for each port independently and
writes them into the RTS Transmit FIFO.
Received RTS values are written to the port specific RTS Receive FIFO to compensate
cell delay variation. RTS values for each port are processed at a frequency equal to the
SRTS period (8 cells). ACM values are processed immediately by the corresponding
PLL.
4.5.2
This block generates 32-bit control frames that are used for communication with the rest
of the system.
For synchronization with the system the received synchronization signal PDSYN is used.
However, if this signal can’t be extracted from the received bit stream by the frame
receiver, the frames are generated by means of an internal synchronization counter.
The frame output is put in tri-state during power down of the internal interface. As soon
as the internal synchronization counter is synchronized on PDSYN signal, the frame
output is enabled.
4.5.3
This block is implemented twice. Once for SRTS and ACM data via port SDOD and once
for the “reset SRTS logic” command via port SDOR.
Data Sheet
Clock
Clock
Line
Line
lc8
1
0
Microprocessor Interface, Test and Control
Data Flow
Frame Generator
Frame Receiver
PLL
lgc
FILTER
0
1
32.768 MHz
Block Diagram of the ICRC
PLL
2.43 MHz
generation
SRTS
ACM
RTS
PLL
PLL
Loopback 1
ena
Receive
0
1
FIFO
RTS
RTS
rtsi
rtso
lgs
ena
1
0
0
1
74
lpcr
0
1
Buffer Filling
Transmit
(ACM)
2.43 MHz
FIFO
PXB4219 / PXB4220 / PXB4221
RTS
RTS
Receiver 1
Receiver 2
Generator
Fractional
Divider
Frame
Frame
Frame
Operational Description
lptu
lptd
1
0
1
0
lprd
0
1
lpru
2002-05-06
0
1
Recovery
SDI
SDOR
PDSYN
SDOD
SCLK
CLK52
RFCLK
Interface
Clock
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