pdiusbd12pwdh NXP Semiconductors, pdiusbd12pwdh Datasheet - Page 9
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pdiusbd12pwdh
Manufacturer Part Number
pdiusbd12pwdh
Description
Usb Interface Device With Parallel Bus
Manufacturer
NXP Semiconductors
Datasheet
1.PDIUSBD12PWDH.pdf
(39 pages)
- Current page: 9 of 39
- Download datasheet (186Kb)
Philips Semiconductors
8. Endpoint description
PDIUSBD12_9
Product data sheet
The PDIUSBD12 supports DMA transfer in single address mode and it can also work in
dual address mode of the DMA controller. In single address mode, the DMA transfer is
done using the DREQ, DMACK_N, EOT_N, WR_N and RD_N control lines. In dual
address mode, pins DMREQ, DMACK_N and EOT_N are not used; instead CS_N,
WR_N and RD_N control signals are used. The I/O mode transfer protocol of the
PDIUSBD12 needs to be followed. The source of the DMAC is accessed during the read
cycle and the destination during the write cycle. Transfer needs to be done in two separate
bus cycles, temporarily storing data in the DMAC.
The PDIUSBD12 endpoints are sufficiently generic to be used by various device classes
ranging from imaging, printer, mass storage and communication device classes. The
PDIUSBD12 endpoints can be configured for four operating modes, depending on the Set
Mode command. The four modes are:
Mode 0
Mode 1
Mode 2
Mode 3
Non-isochronous transfer (Non-ISO mode)
Isochronous output only transfer (ISO-OUT mode)
Isochronous input only transfer (ISO-IN mode)
Isochronous input and output transfer (ISO-I/O mode)
Rev. 09 — 11 May 2006
USB peripheral controller with parallel bus
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PDIUSBD12
9 of 39
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