pdiusbd12pwdh NXP Semiconductors, pdiusbd12pwdh Datasheet - Page 14

• Manufacturer Part Number: pdiusbd12pwdh
• Description: Usb Interface Device With Parallel Bus
• Manufacturer: NXP Semiconductors

Philips Semiconductors
PDIUSBD12_9
Product data sheet
Table 5.
Bit
7 to 6 ENDPOINT
4
3
2
1
Fig 7. Set Mode command, clock division factor byte: bit allocation
Symbol
CONFIGURATION
SoftConnect
INTERRUPT
MODE
CLOCK RUNNING
NO LAZYCLOCK
For bit allocation, see
Set Mode command, configuration byte: bit allocation
7 6 5 4 3 2
0 0
Rev. 09 — 11 May 2006
X X
Table
Description
These two bits set endpoint configurations as follows:
Logic 1 indicates that the upstream pull-up resistor will be connected
if V
be connected. The programmed value will not be changed by a bus
reset.
Logic 1 indicates that all errors and ‘NAK’ are reported and will
generate an interrupt. Logic 0 indicates that only OK is reported. The
programmed value will not be changed by a bus reset.
Logic 1 indicates that internal clocks and PLL are always running
even during the suspend state. Logic 0 indicates that the internal
clock, crystal oscillator and PLL are stopped, whenever not needed.
To meet the strict suspend current requirement, this bit must be set to
logic 0. The programmed value will not be changed by a bus reset.
Logic 1 indicates that CLKOUT will not switch to LazyClock. Logic 0
indicates that CLKOUT switches to LazyClock 1 ms after the
SUSPEND pin goes HIGH. LazyClock frequency is 30 kHz
The programmed value will not be changed by a bus reset.
Mode 0 (Non-ISO mode)
Mode 1 (ISO-OUT mode)
Mode 2 (ISO-IN mode)
Mode 3 (ISO-I/O mode)
For details, see
BUS
1 0
6.
is available. Logic 0 means that the upstream resistor will not
1
1
0
1
Section
Power-on value
CLOCK DIVISION FACTOR
reserved
SET_TO_ONE
SOF-ONLY INTERRUPT MODE
USB peripheral controller with parallel bus
8.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
004aaa800
PDIUSBD12
40 %.
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