aduc847bs8-3 Analog Devices, Inc., aduc847bs8-3 Datasheet - Page 24

• Manufacturer Part Number: aduc847bs8-3
• Description: Microconverter, 10-channel 24-bit Adc With Embedded 62kb Flash Mcu
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
ADCMODE (ADC Mode Register)
Used to control the operational mode of the ADC.
SFR Address
Power-On Default Value 10H
Bit Addressable
Table IX. ADCMODE SFR Bit Designations
NOTES
1. Any change to the MD bits will immediately reset both ADCs. A write to the MD2–0 Bits with no change is also treated as a reset.
2. Once ADCMODE has been written with a calibration mode, the RDY0/1 bits (ADCSTAT) are reset and the calibration commences. On completion, the appropriate calibration
3. Calibrations are performed at user selected SF (see SF SFR) value.
REV. PrA 05/03
Bit
7
6
5
4
3
2
1
0
registers are written, the relevant bits in ADCSTAT are written, and the MD2–0 bits are reset to 000 to indicate the ADC is back in power-down mode.
Name
–––
REJ60
ADCEN

CHOP
MD2
MD1
MD0
Description
Reserved for Future Use
Automatic 60 Hz notch select bit. Setting this bit will place a notch in the frequency response at 60Hz, allowing simultaneous
50 & 60Hz rejection at an SF word of 82. This 60Hz notch can only be set if SF ≥ 68. This second notch is only placed at
60Hz if the ADC clock is at 32.768kHz.
ADC Enable.
Set by the user to enable the ADC and place it in the mode selected in MD2–MD0 below.
Cleared by the user to place the ADC in power-down mode.
Reserved for Future use
Chop Mode Disable
Set by the user to disable Chop Mode on the ADC allowing greater ADC data throughput .
Cleared by the user to enable Chop Mode on the ADC.
Primary and Auxiliary ADC Mode bits. These bits select the operational mode of the enabled ADC as follows:
MD2 MD1
0
0
0
0
1
1
1
1
D1H
No
0
0
1
1
0
0
1
1
MD0
0
1
0
1
0
1
0
1 System Full-Scale Calibration
is automatically connected to the enabled ADC input(s) for this calibration.
User should connect system zero-scale input to the enabled ADC input(s) as selected by
CH3-CH0 bits in the ADCCON2 Register.
User should connect system full-scale input to the enabled ADC input(s) as selected by CH3-CH0
and bits in the ADCCON2 Register.
ADC Power-Down Mode (Power-On Default)
Idle Mode.
Single Conversion Mode
Continuous Conversion
Internal Zero-Scale Calibration
Internal Full-Scale Calibration
System Zero-Scale Calibration
In Idle Mode, the ADC filter and modulator are held in a reset state although the modulator clocks
are still provided.
In Single Conversion Mode, a single conversion is performed on the enabled ADC.
On completion of a conversion, the ADC data registers (ADCH/M/L) are updated.
The relevant flags in the ADCSTAT SFR are written, and power-down is re-entered with the
MD2–MD0 accordingly being written to 000.
In Continuous Conversion Mode, the ADC data registers are regularly updated at the selected update
rate (see SF Register).
Internal short automatically connected to the enabled ADC input(s)
Internal or External REFIN+/- or REFIN2+/- VREF(as determined by XREF bits in ADCCON2)
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ADuC847