aduc847bs8-3 Analog Devices, Inc., aduc847bs8-3 Datasheet - Page 20

• Manufacturer Part Number: aduc847bs8-3
• Description: Microconverter, 10-channel 24-bit Adc With Embedded 62kb Flash Mcu
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
ADC CIRCUIT INFORMATION
The ADuC847 incorporates a 10-channel (8-channel on the MQFP
package) 24-bit Σ−∆ ADC. It also includes an on-chip
programmable gain amplifier and digital filtering intended for the
measurement of wide dynamic range, low frequency signals such
as those in weigh-scale, strain-gauge, pressure transducer, or
temperature measurement applications.
The ADuC847 can be configured as four/five fully-differential
input channels or as eight/ten pseudo-differential input channels
referenced to AINCOM. The ADC is buffered and can be
programmed for one of eight input ranges from ±20 mV to ±2.56V.
Buffering the input channel means that the part can handle
significant source impedances on the analog input and that R,C
filtering (for noise rejection or RFI reduction) can be placed on the
analog inputs if required. These input channels are intended to
convert signals directly from sensors without the need for external
signal conditioning.
The ADC employs a sigma-delta conversion technique to realize up
to 24 bits of no missing codes performance (20Hz update rate, chop
enabled). The sigma-delta modulator converts the sampled input
signal into a digital pulse train whose duty cycle contains the
digital information. A Sinc
employed to decimate the modulator output data stream to give a
valid data conversion result at programmable output rates. The
signal chain has two modes of operation, CHOP enabled and
CHOP disabled. The CHOP bit in the ADCMODE register enables
and disables the chopping scheme.
Signal Chain Overview (CHOP Enabled, CHOP = 0)
With CHOP =0, chopping is enabled, this is the default and gives
optimum performance in terms of drift performance. With
chopping enabled, the available output rates vary from 5.35 Hz to
105 Hz. A block diagram of the ADC input channel with chop
enabled is shown in Figure 7.
The sampling frequency of the modulator loop is many times
higher than the bandwidth of the input signal. The integrator in the
modulator shapes the quantization noise (which results from the
analog-to-digital conversion) so that the noise is pushed toward
one-half of the modulator frequency. The output of the sigma-delta
modulator feeds directly into the digital filter. The digital filter then
band-limits the response to a frequency significantly lower than
one-half of the modulator frequency. In this manner, the 1-bit
output of the comparator is translated into a band limited, low noise
output from the ADuC847 ADC.
The ADuC847 filter is a low-pass, Sinc
primary function is to remove the quantization noise introduced at
the modulator. The cut-off frequency and decimated output data
rate of the filter are programmable via the SF word loaded in the
TABLE IV: Typical Output rms noise (µV) vs Input Range and Update Rate for the ADuC847 with chopping Enabled.
SF
Word
REV. PrA 05/03
255
13
69
Data Update
Rate (Hz)
105.03
19.79
5.35
3
programmable low-pass filter is then
±20 mV
1.50
0.60
0.35
3
or (sinx/x)
±40 mV
1.50
0.65
0.35
3
filter whose
±80 mV
1.60
0.65
0.37
20
±160 mV
1.75
0.65
0.37
filter register. The complete signal chain is chopped resulting in
excellent dc offset and offset drift specifications and is extremely
beneficial in applications where drift, noise rejection, and optimum
EMI rejection are important factors.
With chopping, the ADC repeatedly reverses its inputs. The
decimated digital output words from the Sinc
a positive offset and negative offset term included. As a result, a
final summing stage is included so that each output word from the
filter is summed and averaged with the previous filter output to
produce a new valid output result to be written to the ADC data
register. The programming of the Sinc
restricted to an 8-bit register called SF, the actual decimation factor
is the register value times 8.The decimated output rate from the
Sinc
where
f
SF is the decimal equivalent of the word loaded to the filter
register.
f
The chop rate of the channel is half the output data rate:
As shown in the block diagram, the Sinc
contain +V
This offset is removed by performing a running average of two.
This average by two means that the settling time to any change in
programming of the ADC will be twice the normal conversion
time, while an asynchronous step change on the analog input will
not be fully reflected until the third subsequent output.
The allowable range for SF (Chop Enabled) is 13 to 255 with a
default of 69 (45H). The corresponding conversion rates, RMS and
Pk-Pk noise performances are shown in Table IV & Table V. Note
that the conversion time increases by 0.732 ms for each increment
in SF.
With chopping enabled the ADC noise performance is the same as
that of the ADuC834.
Input Range
ADC
MOD
3
in the ADC conversion rate.
is the modulator sampling rate of 32.768 kHz.
filter (and the ADC conversion rate) will therefore be:
±320 mV
3.50
0.65
0.37
OS
and –V
t
f
SETTLE
ADC
±640 mV
OS
f
, where V
4.50
0.95
0.51
CHOP
=
=
1
3
×
f
=
ADC
8
2
OS
2
×
±1.28 V
1
×
is the respective channel offset.
ADuC847
SF
6.70
1.40
0.82
=
1
f
ADC
2
×
3
×
3
filter outputs alternately
f
t
3
MOD
ADC
decimation factor is
filter, therefore, have
±2.56 V
11.75
2.30
1.25