aduc847bs8-3 Analog Devices, Inc., aduc847bs8-3 Datasheet
aduc847bs8-3
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aduc847bs8-3 Summary of contents
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... Portable Instrumentation, Battery Powered Systems 4-20mA Transmitters Data Logging Precision System Monitoring FUNCTIONAL BLOCK DIAGRAM One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 system, provided that the system ADuC847 www.analog.com © 2003 Analog Devices, Inc. All rights reserved ...
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Preliminary Technical Data SPECIFICATIONS (AVDD = 5.25 V, DVDD = 5.25 V, REFIN(+) = 2.5 V, REFIN(–) = AGND; AGND = DGND ...
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Preliminary Technical Data EXTERNAL REFERENCE INPUTS 2 REFIN(+) to REFIN(–) Range Average Reference Input Current Average Reference Input Current Drift ‘NO Ext. REF’ Trigger Voltage Common Mode DC Rejection Common Mode 50/60Hz Rejection Normal Mode 50/60 Hz Rejection PARAMETER ADC ...
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Preliminary Technical Data CRYSTAL OSCILLATOR (XTAL 1AND XTAL2) 2 Logic Inputs, XTAL1 Only V , Input Low Voltage INL V , Input Low Voltage INH XTAL1 Input Capacitance XTAL2 Output Capacitance LOGIC INPUTS All Inputs except SCLOCK, RESET 2 and ...
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FLAH/EE MEMORY RELIABILITY CHARACTERISTICS 16 Endurance 17 Data Retention POWER REQUIREMENTS Power Supply Voltages AV 3V Nominal Nominal Nominal Nominal DD 5V POWER CONSUMPTION 18, 19 Normal Mode DV Current DD ...
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Preliminary Technical Data 12 Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40 °C, +25°C, +85°C, and +125°C. Typical endurance at 25°C is 700 Kcycles. 13 Retention lifetime equivalent at junction temperature ...
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ABSOLUTE MAXIMUM RATINGS ( 25°C unless otherwise noted AGND DGND AGND DGND 2 AGND to DGND Analog Input Voltage to ...
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Preliminary Technical Data MODEL Temperature Range ADuC847BS62-5 -40 ADuC847BS62-3 -40 -40 ADuC847BCP62-5 ADuC847BCP62-3 -40 ADuC847BCP32-5 -40 ADuC847BCP32-3 -40 -40 ADuC847BCP8-5 ADuC847BCP8-3 -40 EVAL-ADuC847QS EVAL-ADuC847QSP CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on ...
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Pin No: Pin No: Pin 52-MQFP 56-CSP Mnemonic 1 56 P1.0/AIN0 2 1 P1.1/AIN1 3 2 P1.2/AIN2/REFIN2 P1.3/AIN3/REFIN2 AVDD 6 5 AGND --- 6 AGND 7 7 REFIN REFIN P1.4/AIN4 10 10 ...
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Preliminary Technical Data Pin No: Pin No: Pin 52-MQFP 56-CSP Mnemonic 12 12 P1.7/AIN7/IEXC2 13 13 AINCOM 14 14 ---- ---- 15 AIN8 ---- 16 AIN9 15 17 RESET 16-19 18-21 P3.0 22-25 24- P3.0/RXD 17 19 P3.1/TXD ...
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Pin No: Pin No: Pin 52-MQFP 56-CSP Mnemonic P2 P2.0/SCLOCK (SPI P2.1/MOSI 30 32 P2.2/MISO 31 33 P2.3/SS/ P2.4/T2EX 37 40 P2.5/PWM0 38 41 P2.6/PWM1 39 ...
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Preliminary Technical Data Pin No: Pin No: Pin 52-MQFP 56-CSP Mnemonic P0 Input Output Supply. Pin numbers subject to change. REV. PrA 05/03 Type* Description P0.7 ...
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COMPLETE SFR MAP Figure 2 below shows a full SFR memory map and the SFR contents after RESET. NOT USED indicates unoccupied SFR locations. Unoccupied locations in the SFR address space are not implemented; i.e., no register exists at this ...
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Preliminary Technical Data INTRODUCTION The ADuC847 is a 12.58MIPs 8052 core upgrade to the ADuC834 and is very similar to the ADuC845. It includes additional analog inputs for applications requiring more ADC channels as does the ADuC845 but removes the ...
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INSTRUCTION TABLE Mnemonic Description Arithmetic ADD A,Rn Add register to A ADD A,@Ri Add indirect memory to A ADD A,dir Add direct byte to A ADD A,#data Add immediate to A ADDC A,Rn Add register to A with carry ADDC ...
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Preliminary Technical Data Mnemonic Description MOV dir,A Move A to direct byte MOV Rn, dir Mov register to direct byte MOV dir, Rn Move direct to register MOV @Ri,#data Move immediate to indirect memory MOV dir,@Ri Move indirect to direct ...
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MEMORY7 ORGANISATION The ADuC847 contains 4 different memory blocks namely: - 62k/30k/6k Bytes of On-Chip Flash/EE Program Memory - 4kBytes of On-Chip Flash/EE Data Memory - 256 Bytes of General Purpose RAM - 2kBytes of Internal XRAM (1) Flash/EE Program ...
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Preliminary Technical Data The upper 1792 bytes of the internal XRAM can be configured to be used as an extended 11-bit stack pointer. By default the stack will operate exactly like an 8052 in that it will rollover from FFh ...
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Program Status Word (PSW) The PSW SFR contains several bits reflecting the current status of the CPU as detailed in Table I. SFR Address Power ON Default Value Bit Addressable Table I. PSW SFR Bit Designations Bit Name Description 7 ...
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Preliminary Technical Data ADC CIRCUIT INFORMATION The ADuC847 incorporates a 10-channel (8-channel on the MQFP package) 24-bit Σ−∆ ADC. It also includes an on-chip programmable gain amplifier and digital filtering intended for the measurement of wide dynamic range, low frequency ...
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TABLE V : Peak to Peak Resolution (bits) vs Input Range and Update Rate for the ADuC847 with chopping Enabled SF Data Update Word Rate (Hz) ± 105. 19.79 13.5 255 5.35 14 Signal Chain Overview ...
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Preliminary Technical Data TABLE VI: Typical Output rms noise (µV) vs Input Range and Update Rate for the ADuC847 with chopping disabled. SF Data Update Word Rate (Hz) ± 1365.0 2.47 69 59.36 0.961 255 16.06 0.475 TABLE ...
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If either of the pins is floating or if the applied voltage is below a specified threshold then a flag (NOXREF) is set in the ADC status register (ADCSTAT), conversion results are clamped and calibration registers are not updated if ...
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Preliminary Technical Data ADCMODE (ADC Mode Register) Used to control the operational mode of the ADC. SFR Address D1H Power-On Default Value 10H Bit Addressable No Table IX. ADCMODE SFR Bit Designations Bit Name Description 7 ––– Reserved for Future ...
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ADCCON1 (ADC Control Register) ADCCON1 is used to configure the ADC for Buffer, unipolar or bipolar coding and ADC range configuration. ADCCON1 ADC Control SFR SFR Address D2H Power-On Default Value 07H Bit Addressable No Table X. ADCCON1 SFR Bit ...
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Preliminary Technical Data ADCCON2 (ADC Channel Select Register) ADCCON2 is used to select the channel for the ADC ADCCON2 ADC Channel Select Register SFR Address E6H Power-On Default Value 00H Bit Addressable No Table XI. ADCCON2 SFR Bit Designations Bit ...
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Preliminary Technical Data SERIAL INTERFACE The ADuC847 supports a fully licenced* I I2C interface is implemented as a full hardware slave and software master. SDATA (pin 27 on MQFP package and pin 29 on CSP package) is ...
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Preliminary Technical Data 2 I2CDAT I C Data Register Function The I2CDAT SFR is written to by user code to transmit data, or read by user code to read data just received by the I2C interface. Accessing I2CDAT automatically clears ...
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Table XIII. SPICON SFR Bit De Bit Name Description 7 ISPI SPI Interrupt bit Set by MicroConverter at the end of each SPI transfer Cleared directly by user code or indirectly by reading the SPIDAT SFR 6 WCOL Write ...
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Preliminary Technical Data REV. PrA 05/03 OUTLINE DIMENSIONS 30 ADuC847 ...