aduc847bs8-3 Analog Devices, Inc., aduc847bs8-3 Datasheet - Page 11

• Manufacturer Part Number: aduc847bs8-3
• Description: Microconverter, 10-channel 24-bit Adc With Embedded 62kb Flash Mcu
• Manufacturer: Analog Devices, Inc.

REV. PrA 05/03
52-MQFP
28
36
Pin No:
28
29
30
31
36
37
38
39
32
33
40
41
42
31
39
30
39
Pin No:
56-CSP
30
31
32
33
39
40
41
42
34
35
43
44
45
33
42
P2.7/PWMCLK
P2.0/SCLOCK
P2.0
P2.5/PWM0
P2.6/PWM1
Mnemonic
P2.1/MOSI
P2.2/MISO
P2.3/SS/T2
P2.4/T2EX
XTAL1
XTAL2
PSEN
(SPI)
ALE
Pin
EA
P2.7
Type*
I/O
O
I
Description
Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that
have 1s written to them are pulled high by the internal pull-up resistors, and in
that state can be used as inputs. As inputs, Port 2 pins being pulled externally
low will source current because of the internal pull-up resistors. Port 2 emits
the middle and high order address bytes during accesses to the 24-bit external
data memory space.
Port 2 pins also have various secondary functions described below.
Serial interface clock for the SPI interface. As an input this pin is a Schmitt
triggered input and a weak internal pull-up is present on this pin unless it is
outputting logic low.
Serial master output/slave input data for the SPI interface. A strong internal
pull-up is present on this pin when the SPI interface outputs a logic high. A
strong internal pull-down is present on this pin when the SPI interface outputs
a logic low.
Master Input/Slave Output for the SPI Interface. There is a weak pull-up on
this input pin.
Slave select input for the SPI Interface is present at this pin. A weak pull-up is
present on this pin.
On both package options this pin can also be used to provide a clock input to
Timer 2. When Enabled, counter 2 is incremented in response to a negative
transition on the T2 input pin.
This pin can be used to provide a control input to Timer 2. When Enabled, a
negative transition on the T2EX input pin will cause a Timer 2 capture or
reload event.
If the PWM is enabled then the PWM0 output will appear at this pin.
If the PWM is enabled then the PWM1 output will appear at this pin.
If the PWM is enabled then an external PWM clock can be provided at this
pin.
Input to the crystal oscillator inverter.
Output from the crystal oscillator inverter. (see “Hardware Design
Considerations” for description)
External Access Enable, Logic Input. When held high, this input enables the
device to fetch code from internal program memory locations 0000h to F7FFh.
No external program memory access is available on the ADuC847. To
determine the mode of code execution, the EA pin is sampled at the end of an
external RESET assertion or as part of a device power cycle.
EA may also be used as an external emulation I/O pin and therefore the
voltage level at this pin must not be changed during normal mode operation as
it may cause an emulation interrupt that will halt code execution.
Program Store Enable, Logic Output. It is active every six oscillator periods
except during external data memory accesses. This pin remains high during
internal program execution.
PSEN can also be used to enable serial download mode when pulled low
through a resistor at the end of an external RESET assertion or as part of a
device power cycle.
Address Latch Enable, Logic Output. This output is used to latch the low byte
(and page byte for 24-bit data address space accesses) of the address to
external memory during external data memory access cycles. It is activated
every six oscillator periods except during an external data memory access. It
can be disabled by setting the PCON.4 bit in the PCON SFR.
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