saa6713ah NXP Semiconductors, saa6713ah Datasheet - Page 82

• Manufacturer Part Number: saa6713ah
• Description: Xga Analog Input Flat Panel Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.16.6
The transition minimizing programming is done in the
OI_CTRL0 register in the OIF. This section describes how
the OIF pixel input operates with INVA and INVB outputs
for various values of ivsl0 and ivsl1 (register OI_CTRL0).
All modes are designed for double pixel handling.
7.16.6.1
INVA operates with input pixel 0 (means the first of a
couple). This inversion operation considers a total of
18 bits: the 6 high order bits of each colour component of
input pixel 0 (R2 to R7, G2 to G7 and B2 to B7). The input
data of time (n
10 or more bits within the 18 bits have changed from LOW
to HIGH or from HIGH to LOW, then INVA toggles between
HIGH and LOW: if INVA was HIGH at (n
and if it was LOW at (n
bits within the 18 bits have changed from HIGH to LOW or
from LOW to HIGH, then INVA does not toggle. When
INVA is HIGH, all bits (24 bits) of pixel 0 to output (means
data before ‘data to output mapping’) are inverted.
INVB operates with input pixel 1 (means the second of a
couple). This inversion operation considers a total of
18 bits: the 6 high order bits of each colour component of
input pixel 1 (R2 to R7, G2 to G7 and B2 to B7). The input
data of time (n
10 or more bits within the 18 bits have changed from LOW
to HIGH or from HIGH to LOW, then INVB toggles between
HIGH and LOW: if INVB was HIGH at (n
and if it was LOW at (n
bits within the 18 bits have changed from HIGH to LOW or
from LOW to HIGH, then INVB does not toggle. When
INVB is HIGH, all bits (24 bits) of pixel 1 to output are
output inverted.
7.16.6.2
INVA and INVB both operate with input pixel 0 and 1.This
inversion operation considers a total of 36 bits, the 6 high
order bits of each colour component of pixel 0 and 1
(0R2 to 0R7, 0G2 to 0G7, 0B2 to 0B7, 1R2 to 1R7,
1G2 to 1G7 and 1B2 to 1B7). The input data of time
(n
within the 36 bits have changed from LOW to HIGH or from
HIGH to LOW, then both INVA and INVB toggle between
HIGH and LOW. When INVA and INVB are HIGH at
(n
they toggle HIGH. If 18 or fewer bits within the 36 bits have
changed from HIGH to LOW or from LOW to HIGH, then
INVA and INVB do not toggle. When INVA and INVB are
both HIGH, all bits (48 bits) are inverted.
2004 Apr 05
XGA analog input flat panel controller
1) is compared to the data at time n. If 19 or more bits
1), they go LOW, and when they are LOW at (n
T
RANSITION MINIMIZING
Bit ivsl0 = 1 and bit ivsl1 = 0
Bit ivsl0 = 1 and bit ivsl1 = 1
1) is compared to the data at time n. If
1) is compared to the data at time n. If
1), it toggles HIGH. If 9 or fewer
1), it toggles HIGH. If 9 or fewer
1), it goes LOW,
1) it goes LOW,
1),
82
Because there is no previous data for the first data in every
column (horizontal period), the above noted toggle
operations for INVA and INVB, as well as the data
inversion operations are not performed. In the event of first
data output of every column, INVA and INVB are set to
LOW, and data is not inverted.
7.16.6.3
For input pixel, data inversion is similar to when ivsl0 = 1,
ivsl1 = 0, with input pixel 0 and 1 being separated, and the
outputs being driven according to the results of
calculations.
For INVA and INVB signals, the calculations are similar to
when ivsl0 = 1, ivsl1 = 0, but the INVA and INVB outputs
are driven as logical opposites.
7.16.6.4
The INVA and INVB signals are always driven LOW and
data inversion operations are not performed.
7.16.7
The output interface includes a simple frame generator.
It may be useful when the front-end receives no signal, so
no front-end clock is available. The generated frame has
the same dimensions as the picture area. The frame colour
is programmable (OI_FCx). The on screen display is still
working. The generator may be switched on via the
OI_FC_EN register.
B
ACKGROUND AND EMERGENCY FRAME GENERATOR
Bit ivsl0 = 0 and bit ivsl1 = 0
Bit ivsl0 = 0 and bit ivsl1 = 1
SAA6713AH
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