saa6713ah NXP Semiconductors, saa6713ah Datasheet - Page 48

• Manufacturer Part Number: saa6713ah
• Description: Xga Analog Input Flat Panel Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.8
The input interface selects video data either provided by
the ADCs or externally applied and extracts the input
picture for processing. The sample window position and
size is programmable, using vertical and horizontal
synchronization signals as reference. Alternatively, the
picture generator can generate different test pictures with
programmable size and horizontal and vertical blanking
length.
All input interface programming registers are mapped to
the I
7.8.1
The input source is selected by ext_select (register
II_CTRL, address 00H) as shown in Table 29. In case of
parallel RGB input, the R component has to be provided at
ports PA7 (MSB) to PA0 (LSB) in 8-bit format (range
0 to 255), G and B component similarly at
ports PB7 to PB0 and ports PC7 to PC0, respectively. The
input source can only be changed in a functional reset
(see Section 7.3).
The clock signal edge used to sample the data inputs is
specified by ext_clk_edge. If ext_clk_edge is set to logic 1
data is sampled on the rising front-end clock edge;
otherwise on the falling front-end clock edge. If convert_2s
is set to logic 1 the incoming data is expected to be in
2s-complement form from 128 (80H) to +127 (7FH);
otherwise input data is treated as unsigned values from
0 to 255. Data from the internal ADCs is always in
2s-complement form.
To enable the input interface in_form_on has to be set to
logic 1; otherwise no data will be provided for processing.
If the picture generator is active, the input formatter will
always provide generated data.
Table 29 Input source selection
2004 Apr 05
ext_select
XGA analog input flat panel controller
2
C-bus configuration register page 4.
1
0
Input interface
I
NPUT SELECTION
parallel RGB
analog RGB
INPUT SOURCE
48
7.8.2
The synchronization pulses are used to identify the frame
outline. The sync signals for the input interface are
provided by the sync distribution. The complete
description of sync switching options is given in
Section 7.5. If analog or parallel RGB input mode is used,
the vertical synchronization pulse (vsync) is connected to
pin VSYNC and the horizontal synchronization pulse
(hsync) to pin HSYNC. A composite synchronization
signal is connected to pin HSYNC. Pin VSYNC can then
serve as an output for the generated vertical
synchronization pulse.
The polarities of hsync and vsync are defined by vs_pol
and hs_pol. In case of active HIGH polarity, the
corresponding bit has to be set to logic 1; otherwise to
logic 0.
If sync_clk_edge is set to logic 1 all synchronization
signals are sampled with the rising front-end clock signal
edge; otherwise with falling edge.
If delay_vs is set to logic 1, the vsync is delayed in relation
to the hsync to prevent line jitter if both occur at the same
time, which is monitored by the mode detection.
7.8.3
The sample window is defined by in_v_offset, in_h_offset,
in_v_length and in_h_length. The vertical offsets are
measured from the trailing edge of the vsync pulse. The
horizontal offsets are measured from either the first edge
of the hsync pulse if hsync_edge is set to logic 1, or the
second edge if hsync_edge is set to logic 0. Figure 12
shows the horizontal offset for the case hsync_edge is set
to logic 0. If both offsets are set to value 0H, sampling will
start with the first pixel in the first line (see Fig.13).
The length defines width and height of the sampled frame.
The vertical sample offset and length are given in lines and
the horizontal offset and length are measured in pixels.
S
D
YNCHRONIZATION SIGNALS
EFINITION OF SAMPLE WINDOW
SAA6713AH
Product specification