saa6713ah NXP Semiconductors, saa6713ah Datasheet - Page 46

• Manufacturer Part Number: saa6713ah
• Description: Xga Analog Input Flat Panel Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
The interrupt flags are accessible at the global interrupt
state register GC_INT_STAT (FEH) and are readable. The
flags are only cleared (set to LOW) if a logic 1 is written
into the corresponding bit in GC_INT_STAT.
The interrupt conditions are maskable by the
corresponding programming bit in GC_INT_MASK (FDH);
a logic 1 is enabling the particular interrupt condition.
7.7
The integrated triple ADC samples analog RGB signals of
up to 110 MHz with a resolution of 8 bits per colour
component and provide automatic brightness and contrast
control (see Fig.11). The sample clock is generated by the
line-locked PLL (see Section 7.4.3), but can also be
applied externally. The triple ADC is automatically
enabled, when analog RGB is selected as input source.
The time frames for the ADC automatic brightness and
gain control are defined by clamp and gain correction
pulses generated by the input interface. During these
times the ADCs adjust brightness and gain according to
the programmable brightness and contrast values defined
by adc_red_brightness to adc_blue_contrast at registers
ADC_R_BRI to ADC_B_CON (01H to 06H at page 1), that
have to be provided in 2s-complement form between
Not all combinations of contrast and brightness settings
are allowed. Combining very low contrast (low gain)
together with low brightness (more black than black) is not
2004 Apr 05
handbook, full pagewidth
128 (80H) and +127 (7FH).
XGA analog input flat panel controller
Triple analog-to-digital converter
RGB data
CLAMP
GAINC
VHS
gainc_on_delay
Fig.10 Gain adjustment and clamp pulse generation.
gainc_off_delay
clamp_on_delay
clamp_off_delay
46
allowed. These combinations would result in a very low
input DC level, which would result in the clamp circuit
going out of saturation. This would lead to unpredictable
behaviour of the clamp level. The allowed region for the
gain value is limited between 27 and 110.
The clamp and gain correction pulse generation is
programmed via registers II_ADC_CTRL and
II_CLAMP_ON to II_GAINC_OFF (02H to 06H at page 4).
Clamp pulse generation is enabled by clamp_en. The
beginning of the clamp pulse CLAMP is marked by
clamp_on_delay as an offset to the second edge of the
hsync pulse, the end by clamp_off_delay as shown in
Fig.10. The polarity of CLAMP is given with clamp_pol;
logic 1 is HIGH active and logic 0 is LOW active. During
the clamp pulse, that should fall into the hsync backporch,
the ADCs each match the sampled black level output value
to the value given by adc_red_brightness,
adc_green_brightness and adc_blue_brightness
respectively.
The gain correction pulse GAINC is the delayed hsync.
The first edge of the hsync is delayed by gainc_on_delay
and the second edge by gainc_off_delay (see Fig.10). The
polarity is programmed by gainc_pol; logic 1 is HIGH
active and logic 0 is LOW active. The gain correction pulse
generation is enabled by setting gainc_en. During gain
correction the ADC inputs are connected to a reference
voltage and by gain adjustment the output is matched to
adc_red_contrast, adc_green_contrast and
adc_blue_contrast.
SAA6713AH
Product specification
MHC218