saa6713ah NXP Semiconductors, saa6713ah Datasheet - Page 42

• Manufacturer Part Number: saa6713ah
• Description: Xga Analog Input Flat Panel Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.5
The line-locked PLL, input interface and mode detection
are provided with horizontal and vertical synchronization
pulse signals (HSYNC and VSYNC). Signal switching is
controlled by configuration registers SYNC_SEL (18H at
page 0) and SYNC_DIS (19H at page 0). A composite
sync decoder and hsync regeneration can be inserted.
Possible selections and the concerned configuration
parameters are shown in Fig.8 and described more
detailed in the Sections 7.5.1 to 7.5.5.
7.5.1
The composite sync decoder input is selected by sog_en
between the separated SOG provided by the
sync-on-green slicer and a composite sync applied at input
pin HSYNC (see Table 22). The sync-on-green slicer has
to be enabled by setting sync_on_green_en in register
ADC_CTRL (00H at page 1) to logic 1.
2004 Apr 05
handbook, full pagewidth
XGA analog input flat panel controller
Synchronization pulse distribution
C
OMPOSITE SYNC INPUT
CLK
pll_pre_div [ 15:0 ]
PRE-DIVIDER
pll_pre_div_en
FREQUENCY
DETECTOR
PHASE
AND
Fig.7 PLL block diagram.
50 to 320 MHz
OSCILLATOR
42
pll_en
To provide a stable hsync during the vsync, the
sync-on-green slicer might have to be disabled during the
vsync which is performed automatically if sog_vs_disable
is set to logic 1; otherwise the sync-on-green slicer is
constantly enabled.
The composite sync decoder will regenerate hsync and
vsync signals for internal use. Figure 9 shows the
composite sync modes that can be used. The maximum
number of equalizing pulses (csync-3 and csync-4) may
not exceed 30.
Table 22 Composite sync decoder input selection
sog_en
pll_n_div [ 11:0 ]
1
0
n-DIVIDER
pll_m_div [ 1:0 ]
SOG
HSYNC
m-DIVIDER
CSYNC
MHC214
2
SAA6713AH
Product specification
PLL
clock