sta339bws STMicroelectronics, sta339bws Datasheet - Page 47

• Manufacturer Part Number: sta339bws
• Description: 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

STA339BWS
6.8
6.8.1
6.8.2
Table 54.
Audio preset registers (addr 0x0B and 0x0C)
Audio preset register 1 (addr 0x0B)
Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured
to properly fit application specific configurations. AMGC[3:2] is defined in register
coefficients and DRC configuration register (addr 0x31) on page
The AMGC[1:0] bits behave in two different ways depending on the value of AMGC[3:2].
When this value is 00 then bits AMGC[1:0] are defined below in
Table 55.
Audio preset register 2 (addr 0x0C)
Reserved
XO3
D7
D7
0
0
11101100 (0xEC)
11101101 (0xED)
11010111 (0xD7)
11011000 (0xD8)
11011001 (0xD9)
11011010 (0xDA)
11111111 (0xFF)
01100001 (0x61)
AMGC[1:0]
CxV[7:0]
00
01
10
11
Channel volume as a function of CxV[7:0] (continued)
Audio preset gain compression/limiters selection for AMGC[3:2] = 00
Reserved
…
…
…
XO2
D6
D6
0
0
AMGC[1]
User programmable GC
AC no clipping 2.1
AC limited clipping (10%) 2.1
DRC night-time listening mode 2.1
XO1
D5
D5
0
0
AMGC[0]
XO0
D4
D4
0
0
Reserved
AMAM2
D3
D3
0
0
Hard channel mute
Hard channel mute
Mode
-59.5 dB
Volume
-0.5 dB
-60 dB
-61 dB
-62 dB
-80 dB
Reserved
…
…
…
AMAM1
D2
D2
0
0
Table
65.
Register description
55.
Reserved
AMAM0
D1
D1
0
0
EQ
Reserved
AMAME
D0
D0
0
0
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