sta339bws STMicroelectronics, sta339bws Datasheet - Page 27

• Manufacturer Part Number: sta339bws
• Description: 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

STA339BWS
6.1
6.1.1
Configuration register A (addr 0x00)
Master clock select
Table 10.
The STA339BWS supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, and 192 kHz. Therefore the internal clock is:
"
"
"
The external clock frequency provided to the XTI pin must be a multiple of the input sample
frequency (f
The relationship between the input clock and the input sample rate is determined by both
the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor
generating the internal clock and the IR bit determines the oversampling ratio used
internally.
Table 11.
32, 44.1, 48
88.2, 96
176.4, 192
Bit
Input sample rate
FDRB
0
1
2
D7
32.768 MHz for 32 kHz
45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz
49.152 MHz for 48 kHz, 96 kHz, and 192 kHz
0
fs (kHz)
s
R/W
R/W
R/W
R/W
Master clock select
).
Input sampling rates
TWAB
D6
1
RST
1
1
0
1X
00
01
IR
TWRB
D5
1
576 * fs
101
NA
NA
Name
MCS0
MCS1
MCS2
IR1
D4
0
128 * fs
64 * fs
32 * fs
100
Description
Selects the ratio between the input I
frequency and the input clock.
IR0
D3
0
256 * fs
128 * fs
64 * fs
011
MCS[2:0]
MCS2
D2
0
384 * fs
192 * fs
96 * fs
010
Register description
MCS1
512 * fs
256 * fs
128 * fs
D1
1
001
2
S sample
768 * fs
384 * fs
192 * fs
MCS0
D0
000
1
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