sta339bws STMicroelectronics, sta339bws Datasheet - Page 23

• Manufacturer Part Number: sta339bws
• Description: 2.1-channel High-efficiency Digital Audio System
• Manufacturer: STMicroelectronics

STA339BWS
5.3
5.3.1
5.3.2
5.4
5.4.1
5.4.2
5.4.3
5.4.4
Write operation
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA339BWS acknowledges this and the writes for the byte of internal address.
After receiving the internal byte address the STA339BWS again responds with an
acknowledgement.
Byte write
In the byte write mode the master sends one data byte, this is acknowledged by the
STA339BWS. The master then terminates the transfer by generating a STOP condition.
Multi-byte write
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
Read operation
Current address byte read
Following the START condition the master sends a device select code with the RW bit set
to 1. The STA339BWS acknowledges this and then responds by sending one byte of data.
The master then terminates the transfer by generating a STOP condition.
Current address multi-byte read
The multi-byte read modes can start from any internal address. Sequential data bytes are
read from sequential addresses within the STA339BWS. The master acknowledges each
data byte read and then generates a STOP condition terminating the transfer.
Random address byte read
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA339BWS acknowledges this and then the master writes the internal address
byte. After receiving, the internal byte address the STA339BWS again responds with an
acknowledgement. The master then initiates another START condition and sends the device
select code with the RW bit set to 1. The STA339BWS acknowledges this and then
responds by sending one byte of data. The master then terminates the transfer by
generating a STOP condition.
Random address multi-byte read
The multi-byte read modes could start from any internal address. Sequential data bytes are
read from sequential addresses within the STA339BWS. The master acknowledges each
data byte read and then generates a STOP condition terminating the transfer.
I
2
C bus specification
23/77