sta015t-013tr STMicroelectronics, sta015t-013tr Datasheet - Page 41

• Manufacturer Part Number: sta015t-013tr
• Description: Mpeg 2.5 Layer Iii Audio Decoder With Adpcm Capability
• Manufacturer: STMicroelectronics

GPSO_ENABLE
Address: 0xB9 (185)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
This register enable/disable the GPSO interface.
Setting the GEN bit will enable the serial interface for ADPCM data retrieving. Reset GEN bit to disable
GPSO interface.
GPSO_CONF
Address: 0xBA (186)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
GSP: GPSO clock polarity sing this bit the GPSO_SCKR polarity can be controlled. Clearing GSP bit data
GRP: GPSO Request Polarity This bit is used to determine the polarity of GPSO_REQ signal. If GRP bit
ADC_ENABLE
Address: 0xBB (187)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
This register controls if the ADPCM data to be encoded comes from A/D interface or from MP3 bitstream
input interface.
If ADCEN bit is set data to be encoded comes from ADC interface, otherwise data comes from MP3
stream interface
MSB
MSB
MSB
b7
b7
b7
X
X
X
on GPSO_DATA line will be provided on the rising edge of GPSO_SCKR (sampling on falling
edge). Setting GSP bit data are provided on falling edge of GPSO_SCKR (sampling on rising edge)
is cleared data are valid on GPSO_REQ signal high. If this bit is set data are valid on GPSO_REQ
signal low
b6
b6
b6
X
X
X
b5
b5
b5
X
X
X
b4
b4
b4
X
X
X
b3
b3
b3
X
X
X
b2
b2
b2
X
X
X
STA015 STA015B STA015T
GRP
b1
b1
b1
X
X
ADCEN
GEN
LSB
LSB
GSP
LSB
b0
b0
b0
41/55